SU1734097A1 - Concurrent address driver - Google Patents

Abstract

The invention relates to computing and can be used in parallel computing systems with general control and main memory consisting of several independently addressable units. The purpose of the invention is to increase the capacity of the device. In the device containing the block 1 formation of addresses, N adders 2, N blocks 3

Description

b.i 1 K2J --- RF

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comparison, 2N blocks of 4 elements AND, block 5 of forming the sign of the end of addressing, N address shift nodes 6 are introduced. This allows, in accordance with the value of the address shift code, to perform parallel writing — reading the necessary vector elements from the computer's RAM. 9 ill., 1 tab.

The invention relates to computing and can be used in multiprocessor computers with a common main memory consisting of several independently addressable units.

A device for generating an address is known, comprising an index calculation unit, three address registers, three index registers. This device allows calculating the addresses of the access to the RAM without referring to the values of the index to the RAM.

A disadvantage of this device is the low speed of calculating the addresses of accessing RAM.

It is also known an address generation device comprising an address counter, an iteration counter, two switches, an EXCLUSIVE OR element block, a ROM, two OR elements, a pulse shaper, and an additional counter. In this device, depending on the iteration number, the values of the required addresses of the operands are selected from the ROM.

The drawback of the device is the impossibility of forming the necessary number of addresses for accessing the RAM consisting of several independently addressable blocks.

Closest to the invention is a device for parallel generation of addresses comprising an address register group, an index step register group, an address switch, an index switch, adders, a block number register group, a block number switch, an index shift and memory block, a comparison circuit group, an element OR, trigger, register of the maximum index, a group of blocks of elements AND, and the information input of the K-th address register is connected to the K-th input of the device’s initial address (K 1H, where H is the number of initial a Dres), the output of the K-ro address register is connected to the K-th information input of the address switch, the output of which is connected to the first input of the first adder. The output of the R-ro register of the index step is connected to the R-th information input of the index switch (R 1, ..., O, where Q is the number of steps for changing the indices). The input of the maximum allowable device index is connected to the information input of the maximum index register, the output of which is connected to the first inputs of the group comparison circuits, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the installation input of 1 trigger. The output of the latter is connected to

output sign of the end of the addressing device. The device address selection input is connected to the step selection input of the index switch index and is connected to the switch input input of the block number,

the output of which is connected to the shift input of the memory and index shift block, and the i-th input of the initial block number of the device is connected to the i-th input of the block number register (where i 1 ... K), the output of the address switch is connected to the first inputs of the adders from the second by (M-1) -th input of the read permission of which is connected to the I-th input of the selection of the device address group (where I 1 ... M, where M is the number of address cycles

array), the n-th output of the index field of the storage unit and the shift of the indices and the output of the n-th adder are connected to the n-th information inputs of the first and second blocks of the groups of elements I, respectively (n 1 ... N, where

N is the number of concurrently formed addresses), the nth information outputs of which are connected to the nth outputs of the device's lower and higher address bits, the nth output of the comparison circuit

the group is connected to the n-th input of the resolution of issuing information of the first and second blocks of groups of elements I. the n-th output of the index field and the n-th output of the increment field of the address of the storage unit and the shift of the indexes are connected to the second input of the n-th group comparison circuit, n- The output of the field of the increment of the index-memory unit is connected to the second input of the n-th adder. Information entry R-ro index step register

The group is connected to the R-th input of the step of changing the device group index.

In this device, the main addressable memory of the computing system consists of P blocks with independent addressable

chains of the same size. The full address of the main memory cell is formed by two components: the block number (the lower-order bits of the full address) and the cell address in the block (the higher-order bits of the full address). The storage of addressable data in the main memory in the form of a one-dimensional array (vector) is assumed. Moreover, the neighboring elements of the vector have addresses differing by one. The starting address of the cell in the block and the initial block number are sent to the input registers of the device. In addition, the input registers of the device are supplied with the step with which it is necessary to access the elements of the vector, as well as the boundary of the vector. The device generates several (N) addresses in parallel to access the elements of the vector until the generated address reaches the maximum vector boundary. For parallel formation of M addresses in N cycles (where MN P is the number of independently addressable memory blocks), the input is the cell address, vector size, step value with which vector elements are to be read, the block number where the first vector element is located, and at the output of the device, the full values of the addresses are formed (the low-order bits are the block number, the high-order bits are the cell number). The values of M and N can be varied within wide limits.

This device places the adjacent elements of the vector when they are written in another located memory cells. However, there is a need to read vector elements either from additional spaced memory cells (the index step value is one), or from memory cells with a step other than one. The need to sample elements of a vector with a step greater than one occurs, for example, when sampling matrix columns, diagonal matrix elements (matrices in the memory are stored as a set of vectors — rows or vectors — columns). At the same time, for certain values of the step, selectable elements are placed in one memory block. As a result, the memory bandwidth decreases due to the sequential reading of vector elements from this block.

The disadvantage of this device is the inability to place (select) data in accordance with a certain regularity, which leads to a drop in memory bandwidth.

The purpose of the invention is to increase memory throughput by rationalizing the placement of vector elements in memory blocks.

In the device, the generated addresses are shifted according to the code value at the input of the setting of the device address shift code.

5 In this case, the memory capacity when accessing diagonal matrix elements and matrix column elements increases in proportion to the number of memory blocks compared to the prototype. Thus, the technical and economic advantage of the proposed device in comparison with the prototype is an increase in the memory bandwidth by P times, where P is the number of memory blocks.

The goal is achieved by the fact that

a device for parallel address generation, containing an address generation unit, an address completion indication unit, N comparison blocks

0 (where N is the number of concurrently formed addresses), N adders, 2N I blocks, and the output of the 1 st comparison block is connected to the first inputs of the i-ro and (i + 1) -ro blocks of the I elements and the i-th by the entrance

5 termination feature blocks

addressing (i 1 N) control input

the address generation block is the input of selecting the device address group, the i-th output of the address shaping block

0 is connected to the first input i-ro of the adder, the output of which is connected to the second input of the i-ro block of elements I, the output of which is the output of the higher bits of the i-ro address of the device, the output of the (i + N) -ro block

5 elements AND is the output of the lower-order bits of the i-ro address of the device, the N node is entered into the address shift, the first address input of the i-ro address shift node is connected to the output of the i-ro accumulator and to the first input

0 i-ro comparison unit, the second address input - with the input of the device address shift code setting, the information input is connected to the (i + N) -M output of the address generation unit, whose address input is

5, the input of the device index step, the information input — the input of the initial number of the device block, the control inputs of the address shift nodes are combined and are the shift resolution input

0 device addresses, the output of the i-ro address shift node is connected to the second inputs of the i-ro comparison block and the (i + N) -ro AND block of the elements, the third inputs of the AND blocks of the AND blocks are combined and are the input of the output resolution of the device address group, the third the inputs of the comparison units are combined and are the input of the device array edge specification, the second inputs of the adders are combined and are the input of the address assignment

the device cells, the output of the addressing tertiary formation unit is the output of the device address termination indication.

FIG. 1 shows a functional diagram of the device for parallel generation of addresses; in fig. 2 is a functional block diagram of the formation of addresses; in fig. 3 is a functional diagram of the address generation node; in fig. 4-functional scheme of the node address shift; in fig. five

- functional comparison block diagram; in fig. 6 - functional block diagram of the elements And; in fig. 7 and 8 are examples of the placement of information in the RAM; in fig. 9 - time diagrams of the device.

The device (Fig. 1) contains an address generation unit 1, N adders 2.1 - 2.N, N blocks 3.1 - 3.N comparisons, 2N blocks 4.1

-4.2N elements And, block 5 forming the sign of the end of addressing, N nodes 6.1

-6.N shift address. The device also has input 7 for setting the initial block number of the device, input 8 for setting the device index step, input 9 for selecting the device address group, input 10 for setting the cell address of the device, input 11 for specifying the device array boundary, input 12 for specifying the device address shift code, resolution 13 for the address shift, the input 14 of the resolution of the issuance of the address group, the output group of the 15 most significant bits of the address group, the output group of the 16 lower bits of the address group, the output 17 of the sign of the end of device addressing.

Block 1 of the formation of addresses contains (Fig. 2) a group of nodes 18 of the formation of the address 18.

Each address generation node 18 contains (FIG. 3) a memory block 19 and an adder 20.

The address shift node 6 contains (FIG. 4) a memory block 21 and an adder 22,

Comparison unit 3 contains (FIG. 5) a comparison element 23 and an OR element 24, in particular, K 555SP1, K 531SP1 series chips, etc. can be used as comparison elements 23.

Block 4 of elements And contains (Fig. 6) group 25 of three-input elements I.

FIG. 9 are designated: T - a cycle of operation of the device; 7, 8, 10-12, 15 informational signals at the corresponding inputs (outputs) of the device; 9, 13, 14 - control signals at the corresponding inputs of the device.

The device works as follows.

The main addressable memory of the computing system in which the device is intended to be used consists of P (P - integer) blocks having independent

address chains of the same size. The full address of the main memory cell is formed by the block number (lower address bits) and the cell number in the block (higher address bits.

The main feature of the computing system, in which the device is supposed to be used, is that operations are performed on vectors, operands, and the result is a vector

- operand. The vector is understood as an array of data V, consisting of n elements V (0), V (1) V (i) V (n-1), where n means limited memory capacity. The matrix is represented as the aggregate of a certain

numbers of vectors - lines. Vectors are usually located in the memory so that each element of the vector is in one cell, and the numbers of the cells follow either another, or in a certain relationship. The performance of the computing system depends, on the one hand, on the processor's ability to process the operand vectors, and on the other hand, on the memory bandwidth. Memory bandwidth is the number of vector elements written or read into the memory per unit of time. The capacity of the memory is conveniently characterized by the number W of accesses to

OD required to read (write) a specified number of (n) vector elements (n P). Typically, vector elements are located in additional located memory cells (Fig. 7). Read items

vectors are possible either from the subdivisions of the OP cells (with a step h 1), or from the OP cells with a step different from one. In general, the order of sampling of vector elements can be represented as follows: V (i), V (i + h), V (i + 2h) where the step is h 1.

The need to sample the elements of a vector with a step h 1 arises, for example, when sampling the columns of a matrix, the diagonal elements of a matrix, etc. The address of the memory cell when placing the elements of the vector in the subdivided cells consists of two parts. The first part (the lower order bits) defines the number of the memory block, and the second part (the higher order bits) the cell number in the block. If the number of memory modules is equal to Р, then the Kth element of the vector (О К (п-1)) will be placed in the block with the number Mk, determined by the formula Mk KmodP.

The capacity of the memory with such an arrangement of the vector's elements significantly depends on the access step. For example, (Fig. 7), with the access step h 8, the selectable elements of the vector are located in one memory block, as a result of which conflicts arise while simultaneously referring to these elements of the vector. To reduce conflicts, it is proposed to place the vector elements not in the adjacent memory cells, but in cells whose block numbers are determined according to a certain dependence. Such an arrangement of vector elements (Fig. 8) is provided in the device with the help of address shift nodes.

The relationship between the numbers of the vector elements and the numbers of the blocks in which these elements are placed is uniquely established with the help of the relation

MK (K + rK / P) modP, where g is 0.1 (P-1).

In particular, at r 0, the block number is not shifted (Fig. 7) and the block number is formed according to the dependence

Mk KmodP.

The value of r is formed by software and comes from the input 12 of the setting of the device address shift code to the second address inputs of the address shift nodes 6.

The addresses of the operands come from the processor to the inputs 7, 8, 10, 11, 12 devices. The width of the input 10 of the cell address depends on the number of cells in the addressable memory blocks. The input width 8 of the index step setting depends on the possible values of the step of accessing the vector elements. The input width 7 of the initial block number depends on the number of memory blocks and is equal to ModeI, where% | ... L is the largest integer. The input width 12 of the address shift code depends on the number of memory blocks and is equal to Jlog2P. The width of the input 9 of the selection of the address group (M) depends on the number of nodes forming the address 18 in the block 1 forming the addresses and the number of groups (N) of nodes 18 and is determined by the ratio M P / N. The total number of nodes 18 is equal to the number of independently addressable memory blocks (P). The structure of the proposed device allows varying the number of parallel formed addresses (N) within large limits from N 1 to N P. Moreover, with N 1, the operation of the device is reduced to the sequential formation of addresses. The code input to the selection of the device address group 9 is unitary, i.e. on the first addressing signal

from the first bit of bus 9, the read resolution signal is supplied to the N nodes 18 of the first vertical line of blocks 18 (Fig 2); by i-th signal from input 9 through i-th

bus bit signal arrives at the i-th vertical line of nodes 18 of block 1 and so on up to M. If N P, then bus 9 contains one bit, and the device generates P addresses simultaneously. And the device

0 allows you to create an i-th address group at once. The number of comparison blocks 3, adders 2 and address shift nodes 6 is equal to the number of simultaneously formed addresses (N). The bus width of the blocks of the elements of elements AND with the numbers from 4.1 to 4.N is equal to the width of the input 10 of the device. The bus width of the blocks of elements And with numbers from 4. (N + 1) no 4.2N is equal to the width of the input 7 of the device. The number of elements And 25 in

0 blocks 4 are determined by the input bus width (Fig. 6). The number of inputs of the block 5 of the formation of the sign of the end of the addressing (is an OR element) is equal to N. The width of the input is 11 tasks

The 5 bounds of the array is equal to the sum of the digits of the inputs 7 and 10.

From the outputs of adders 2, all bits of the units of the comparison block 3 arrive, and the first address inputs of the nodes

0 address shift Jlog2P | , the lower bits of the formed cell addresses. The first address formed by the device consists of the address of the cell (the high bits of the full address) at the output of the AND block with the number 4.1 and the block number (the lower bits of the full address) at the output of the AND block number 4, (N + 1) .

On the first signal coming from the input 9 of the choice of the group of addresses of the device

0 to the enable input of the address generation unit 1, the first address group is generated at its outputs. And at the outputs from the first to the N-1, groups of the senior bits of the full address are formed, and

5, at the outputs from (N + 1) -ro to 2M, the groups of the lower-order bits of the full address are formed. Groups of low-order bits arrive at the information inputs of nodes 6 of the address shift, and groups of high-order bits arrive

0 to the second inputs of adders 2. The first inputs of adders 2 receive the value of the cell address from input 10 of the device. The groups of higher bits from the outputs of adders 2 are fed to the first inputs of blocks 3 of comparison. The third inputs of the comparison units 3 receive the value of the array boundary from the input 11 of the device. At the first address inputs of the address shift nodes 6, the JlogaPL of the address of the cell formed at the output of the adder 2 arrives.

the inputs of the address shift nodes 6 enters the value of the address shift code from the input 12 of the device. According to the shift resolution signal coming from the input 13 of the device to the enabling input of the address shift nodes 6, the lower bits of the addresses are generated at the output of the nodes 6, which are fed to the second inputs of the comparison blocks 3.

In addition, the generated block numbers are the first groups of inputs of the AND 4 elements. (N + 1) - 4. (2N). From the outputs of the adders, the 2 values of the higher bits of the address (cell addresses) go to the first groups of inputs of the AND 4.1 - 4.N. In the event that the generated address exceeds the value of the array boundary (or reaches it), the i-th comparison unit 3 removes the potential from its output, as a result of which a single signal is generated at output 5 of the output signal 17 at the output of the device .

In addition, from the output of the i-ro of the comparison unit 3, a single potential is removed at the second input of the blocks of the elements 4.1 and 4. (N + i), i.e. the formation of an i-ro address is prohibited. All subsequent generated addresses also exceed the value of the array boundary. The permission signal for issuing a group of addresses coming from the input 14 of the device to the third inputs of the blocks of elements AND from the outputs of the blocks of elements AND from numbers 4.1 to 4.N receives the values of the higher bits of the formed addresses to the group of outputs 15 of the device, and from the outputs of the blocks of elements And with the numbers with 4, (N + 1) and 4.2N, the values of the lower bits of the address group are received per output group 16 of the device. As a result, n addresses are formed. The first cycle of the device (Fig. 9) is over.

In the second cycle of operation of the device and the subsequent ones, they are formed by N consecutive addresses, while at the next cycle the formed address does not exceed the value of the array boundary (or reaches it) and the sign of the end of addressing at the device output 17 is generated. On the signal of the end of the addressing, the device terminates operation, i.e. the feed to the inputs 9.13, 14, respectively, of the signals for selecting the address group, resolution of the shift, resolution of the output of the group of addresses

The node address shift (Fig. 4) works as follows.

From the first and second address inputs of the node 6, the values of the low and high bits of the address are sent to the address input of the memory block 21. The enable input of the memory block 21 from the enable input of node 6 receives a sampling signal, which

The output of the memory block 21 is formed by the pre-recorded value of the block number in accordance with the table.

From the output of block 21, the value of the block number arrives at the first input of the adder 22. The second input of the adder 22 from the information input of the node 6 receives the value of the block number generated in block 1. The adder 22 by bitwise modulo P of the values supplied to the first and second inputs, forms at the node output the value of the block number.

An example of parallel formation of addresses by the device. Suppose that the number of memory blocks is P 8, N 8, M 1; the index step value is eight; the initial value of the cell number is (000) 2; the initial value of the block number is (000) 2; the value of the array border is (1000000) 2.

Example 1 (Fig. 7), the address shift code at the input 12 of the device is (000) 2. The values of the index step and the block number are transferred to the address generation block 1. The signal for selecting an address group. From memory blocks 19 of one (since N P and M 1), the column of address formation nodes 18 in the first operation cycle of the device (Fig. 9) receives cell number values at the first inputs of adders 20 (values are given in binary code)

000 000, 001 000, 010 000, 011 000, 100 000, 101 000, 110000, 111 000.

The second inputs of the adders 20 receives the value of the block number from the input 7 of the device. In the first groups of outputs (from the 1st to the 8th) of block 1, the values of the addressable cells are formed, and on the groups of outputs (from the 9th to the 16th), the values of the block numbers are formed

000 000, 001 000, 010 000, 011 000, 100 000, 101 000, 110000, 111 000, where the first triad is the value of the cell number, and the second is the value of the block number.

The starting cell address value from device input 10 enters the first inputs of adders 2.1 through 2.8, and the second inputs of the adders receive the cell number values generated in block 1. At the output of the adders 2, the values of the older device address groups (cell number in the block) are generated. Since the value at the input 12 of the address offset is (000) 2, then at the output of the blocks 21 of the memory of the address shift nodes 6 zero values of the block numbers are generated by the shift resolution signal from the input 13 of the device, and at the output of the nodes 6 the block numbers are equal to

000, 000, 000, 000, 000, 000, 000, 000.

Since the values of the formed addresses do not exceed the values of the array boundary coming from the device input 11 to the comparison blocks 3, all comparison blocks retain the potential values that allow the formed addresses to pass through the blocks of the I 4 elements. After the receipt of the permission signal, the output of the address group at the outputs of the blocks elements And with numbers from 4.1 to 4.8 form the addresses of the cells (the upper bits of the address - the first triad), and the outputs of the blocks of elements And with the numbers from 4.9 to 4.16 - the values of the numbers of memory blocks (younger th address bits - second triad)

000 000, 001 000, 010 000, 011 000, 100 000, 101 000, 110000, 111 000.

In the second cycle of operation of the device, the following eight addresses are formed similarly, but their values exceed the values of the array boundaries and the comparison blocks with numbers from 3.1 to 3.8 remove the permitting noTet from the blocks of AND elements from 4.1 to 4.16. In addition, the signal, taken from the outputs of the comparison units, through the OR element is fed to the output of the device, which leads to the termination of the further supply of signals to the inputs 9, 13, 14 of the device.

All selectable elements of the vector (V (0), V (8), V (16) V (56)) are located in the memory block with the number (000) 2 (Fig.7). Thus, in this case, when sampling with a step equal to 8, the memory capacity will be minimal (one element of the vector in one cycle of circulation).

Example 2 (Fig. 8). The value of the address shift code is exactly (001) 2. The operation of the device is similar to the operation of the device in Example 1, except that the block 21 of the memory on the first adder codes of 22 nodes from 16.1 to 16.8 receives the values of the block numbers, and on the second inputs of adders 22 - the values of block numbers from the outputs of block 1 are formed by m addresses. The following block number values will be generated at the outputs of the address shift nodes 16

000,001,010,011, 100, 101, 110111.

On the output groups 15, the addresses of the cells are formed (the first triads), and on the groups of the outputs 16 - the values of the memory block numbers (the second triads)

000000, 001 001, 010010, 011 011, 100 100, 101 101, 110 110, 111 111.

In this case, the selectable elements of the vector are in different memory blocks (Fig. 8). The capacity of the memory will be maximum and equal to 8

vector elements.

Claims (1)

Apparatus of the Invention A device for the parallel generation of addresses, comprising an address generation unit, a formation unit the sign of the end of addressing, N blocks of comparison (where N is the number of concurrently formed addresses), N adders, 2N blocks of I elements, and the output of the i-ro block of the comparison is connected to the first inputs i-ro and (i + N) -ro blocks of the elements I and the i-th input of the block forming the sign of the end of addressing, (i 1 N) controlling the input of the address generation unit is an input for selecting a device address group, The i-th output of the address generation unit is connected to the first input of the i-ro adder, the output of which is connected to the second input of the i-ro element block, whose output is the input of the higher bit of the i-ro address of the device, output (i + N) - ro block of elements I is the output of the lower bit of the 1st address of the device, characterized in that, in order to increase the capacity of the device, N nodes are entered into it address shift, the first address input of the i-ro address shift node is connected to the output of the 1st adder and the first input of the comparison unit, the second address input is connected to the input of the device address shift code, the information input is connected to (i + N) -M the output of the address generation block whose address input is the input of the device index step setting, the information input inputs of the initial block number of the device, the control input of the address shift node i-ro is the address input of the device address shift, output of the shift node i-ro coupled to second inputs of the i-ro the comparator and (i + N) -ro of the AND block, the third inputs of the AND blocks are combined and are the enable input of the output of the device address group, the third inputs of the comparison blocks are combined and are the input of the device array edge specification, the second adders inputs are combined and setting the cell address of the device, the output of the block forming the sign of the end of addressing ending device addressing. Dx.8 Bx.9: Jw.2 ND BA 6 NABA.2 Fig.Z H, 6v6 ON 0SH.2 to.tt OTSV.5 25 Fig 6 S about s at  S f DC about D ABOUT. Fig7 four 1 G, I  Jl 25 25