SU1734093A1 - Logic analyzer - Google Patents

Abstract

The invention relates to computing and can be used to monitor and debug digital devices and microprocessor systems. The goal — improving the reliability of registering information coming from the monitoring object — is achieved by introducing a start delay feature selector, a restart feature selector to the analyzer, and also achieved by starting a block with m trigger channels, where m is the number of trigger levels. At the same time, the device allows analyzing data coming from information inputs in real time and tracking m trigger levels with specifying the time interval between trigger levels, with the trigger condition, delay parameters being monitored at each trigger level, and controlling the appearance of a prohibited feature . This makes it easy to choose the device startup mode for controlling information sequences of the secondary structure (containing branches, cycles) accompanying the operation of microprocessor devices, and, consequently, increase the productivity of the developer, microprocessor debugger. 2 hp f-ly, 4 ill. (Ls

Description

The invention relates to computing and can be used as a means of controlling and debugging digital devices and microprocessor systems.

The purpose of the invention is to increase the reliability of the control.

Figure 1 shows the structural diagram of the analyzer; Figures 2, 3, and 4 are examples that implement the trigger feature selector, the memory management unit, and the sync pulse generator.

The analyzer (FIG. 1) contains a buffer register 1, a memory block 2, a synchronization pulse shaper 3, a selector 4 for-. launch signs, selector 5 signs of delayed start, selector 6 signs of restart, block 7 of memory management, block 8 of start, which contains an element

OR 9, t-1 elements AND 10, delay element 11, m launch channels 12, each of which contains trigger 13, first 14 and second 15 AND elements, AND-NOT 16 element, IL-AND-17 element, And- NOT 18, trigger 19 and counter 20.

1 also shows the inputs of the analyzer: a group of informational 21 and clock inputs 22, a group of inputs specifying the operation mode of the analyzer 2329; analyzer outputs: groups of information outputs 30 and 31 and inputs and outputs 32, .., 47 blocks.

Groups of informational 21 and clock inputs 22 of the analyzer are used to receive informational and synchronizing signals from the control object. Input Groups

x |

WITH

Ј

about about

set analyzer operation mode 23

29 and information output groups 30, 31 serve to connect the analyzer to the controller I / O unit. A group of inputs 23, 24 and 25 sets the mode of generating start signs, signs of start delay and restart signs: the value of the signs and conditions of their strokes with clock pulses, through group 26 - masking of start signs, counters 20 and restart signs, through group 27 - task digital trigger delay values for each of channels 12; through group 28, the resolution of the pause between trigger levels with a duration longer than the period of the clock signal (maximum pause). Through the group of inputs 29 of the analyzer, the starting address is set for memory block 2 and the operation mode of block 7 is set: positive or negative trigger. Through the group of information outputs 30, the word analyzer status and the address of the memory 2 memory blocks are read into the analyzer controller, and through the group 31, the contents of memory 2 memory.

The selector 4 (FIG. 2) of the trigger signs comprises an associative memory block 48, a multiplexer 49, a group of multiplexers 505050 and a group of elements And 511, ..., 51 5.

Selectors 5 and 6 have a structure identical to that of selector 4.

The memory management unit 7 comprises a counter 52, a switch 53, triggers 54-57, and drivers 58 and 59.

Shaper 3 consists of n channels

60 (n-size group of inputs 22), each of which includes a threshold element

61 and pulse shaper 62. In addition, the imaging unit 3 contains the element OR 63.

The analyzer allows data collection from information inputs 21 during synchronization via inputs 22 from the control object in the positive start mode — recording the input states from the start signal to the memory block 2 overflow, and in the negative start mode, recording from the start signal to generating trigger signal. In the case of a negative start, the contents of memory block 2 may be repeatedly updated, and after stopping, the state immediately preceding the generation of the trigger signal is retained in the memory block. The trigger signal arriving at block 7 via line 38 is the result of the operation of m start channels 12 of block 8 by analyzing the sign signals that are received at block 8 of start from groups 32. 33 and 34 of the outputs of selectors 4, 5 and 6, if

The required signs appeared on the information inputs of 21 analyzers.

The operation of the i-ro launch channel 12 i can be described using an expression like:

Si Mvi VV | - MNiYlDi Njl.O)

  Ri

t

where Si is the signal of the i-th trigger level, generated by channel 12 | run on input 43i

element and 10i;

Vi is the trigger indication signal from output 32 | the selector 4 to the trigger input of the 19th | of the 12i start channel;

DI is the signal of the sign of the delay, postayuschy from the output 33 of the selector 5 to the element AND-NOT 16 channel 12

Ri - signal restart sign, coming from the output 34j of the selector 6 to the first 14 element VI of channel 121;

M | - the value (code) of the digital delay, counted by the counter 20 in the 1st launch channel 12 |. The delay code is set via the 1st subgroup of the group of inputs 27 of the analyzer mode setting;

MVI, MNI, MRI are the masking signals of the start sign Vj, the start up delay DI-Ni and the restart sign RI, coming from the corresponding inputs of the group of inputs 26 of the analyzer mode, respectively, to the input of the trigger setup 19, the input of the AND-18 element and the input of the first AND element 14 1st launch channel 12 |.

The signal of the 1st trigger level to the input 43 of the element And 10 comes from the direct output

trigger 13 and is generated if after the appearance at exit 32 | the selector 4 of the start sign signal, which translates trigger 19 into the state log. 1, and thereby allowing the passage of the signal of the trigger delay sign from the output 33 | the selector 5 through the element AND-E E 16 to the counter 20 during the time interval, while the indications of the delay are counted by the counter 20, the sign signal does not appear

restart at exit 34 | the selector 6. Otherwise, the reset 19 and the counter 20 are reset to an initial state by a restart sign signal passing through the elements AND 14, IL AND NOT 17, and

then again only after the arrival of the signal

a start sign will start a new delay countdown. Any of the restart trigger signs and delay countdown signals can be excluded from the analysis due to the masking signals received through a group of inputs 26. Here, the operation of the launch channel 12j is changed and described by one of the expressions:

Si Vi - when masking the delay DIxNi;

Si Di x Ni - when masking the signals of the sign of the start and restart RI;

Si x NI - when masking the signal sign restart RI;

Si - when masking signalL- kg

PA sign start VLSI 1 - when masking the signal sign start Vi and delay DI x NI.

The signal of the 1st trigger level from the direct output of the trigger 13 channel 12 | is fed to the data input trigger 19 of the next channel 12n-1. thereby resolving the tracing of signs of the next (i + 1) -ro level. Thus, the trigger signal at output 38 of block 8 will be generated by channel 12t only after the alternate operation of the previous channels 12i12m, thereby

the sequence of attributes is tracked (in the absence of masking of any components in expression 1)) nycK7Widi x N2 ...:

2

V,

m

Rm

The direct output signal of the trigger 12 of the 12t channel is, for block 7, the signal by which the recording of information in block 2 begins or ends.

When a trigger indication signal appears at the output 32i + t of the selector 4, trigger 19 (1 + 1) -th trigger channel is triggered and from the inverse output of trigger 19, the signal arrives at input 44i + i of the And 10i element, which provides an estimate of the time interval T ( ticks) from the generation of the 1st trigger level signal (at input 43i to the appearance of a signal at input 44 | +1 (actually to the appearance of the trigger indication signal of the i + 1th trigger channel). The operation of block 8 can be described as a whole nycK-Vi-4-Di x. N2 --- -THEATS-T -fiTTz.

sh

rfleTj-2, T2, h., are the masking signals of an interval of arbitrary duration T arriving at And 10 elements through a group of inputs 28 of the analyzer.

If the signal Ti, 1 + 1, arriving at the input of the 1st element AND 10i from the corresponding input of the group of inputs 28, is high, this sets the mode of operation for the 1st and 1 + 1 th launch channels - without resolving the interval to an arbitrary the duration T (the time interval is longer than the period of the clock signal) between the moment of generation of the signal of the 1st trigger level and the appearance of the trigger sign signal f + 1-ro. This means that after generating the signal of the 1st level, the formation of the signal i + 1 of the trigger level, i.e. there should be a trigger indication signal at the gate input of the trigger trigger 19 i + 1 trigger channel 12 | -c, after which the signal from the inverse output

0 trigger 19, entering the input element AND 10i, prohibits the clock signal from input 45 of element 10. The reset signal to the initial state of the trigger channels at the output of the element OR 9 is not generated, the tracking of I + 1 trigger level signs will continue . If, after generating the signal of the 1st trigger level, at the time of the occurrence of the next clock signal at input 45, the trigger 19 l + 1-ro channel of the trigger does not work, then the clock signal passes through the AND 10 element, the OR 9 element and from its output 47 will go to each channel 12i12m. setting them to their original state. Sequence tracking is on the 5th level from the first level. If the signal is Ti. 1 + 1 is low, then the operation of the 1st element And 10i is prohibited (masked), and the time interval of duration T, is longer than the period of the clock signal between the moment

0 generation of the signal of the 1st trigger level and the appearance of the trigger indication signal i + 1 level does not lead to a reset

5 start channels condition 12i12P.e

Claims (3)

Claim 1. A logic analyzer comprising a startup unit, a memory management unit, 0 memory block, trigger feature selector, synchronization pulse generator and buffer register, the group of information inputs of which is the group of information inputs of the analyzer, group „ 5 bit outputs of the buffer register are connected to the group of information inputs of the memory block and the first group of information inputs of the trigger feature selector; the input of the buffer register is connected to 0, the first output of the synchronization pulse generator, the group of clock inputs of which is the group of clock inputs of the analyzer, the group of outputs of the trigger feature selector is connected to the first 5, a group of information inputs of the trigger unit, a group of inputs for masking the signs and the second group of information inputs for the trigger signs selector are the first and second groups of inputs of the analyzer modes, the output of the trigger block is connected to the trigger input of the memory control unit, the group of information inputs of which are the third group of inputs of the analyzer mode assignment, the first group of outputs of the memory control block is connected to the address inputs of the memory block, the control input of which is connected to the first output of the memory management unit, a group of outputs of the memory unit and the second group of outputs of the memory management unit form the first and second groups of information outputs of the analyzer for reading the recorded information and the word of the analyzer state, respectively, in order to increase the validity of the control, a start delay feature selector and a restart feature selector are entered into it, and the start block contains a group of (t-1) AND elements, an OR element, a delay element, and m start channels ska (t is the number of trigger levels), each of which includes the first trigger and the second trigger, a counter, two AND elements, two AND-NOT elements and an OR-NOT element, and the clock input of the first trigger of the 1st trigger channel is The first input of the first group of information inputs of the start block, the first inputs of the first AND-NOT elements of the start channels form the second group of information inputs of the start block and are connected to the output group of the trigger delay selector signs, the first inputs of the first elements of the start channels form the third information group These inputs of the start block are connected to the output group of the restart feature selector, the second inputs of the first AND elements, the first inputs of the second NAND elements and the installation inputs of the first trigger m and the start channels form a group of the mask inputs for the start block, the information input of the first trigger of the first start channel is the enable input of the trigger unit and is connected to the second output of the memory control block whose clock input and input of the delay element are connected to the first output of the sync pulse generator Onization, the output of the delay element is connected to the first inputs of the AND elements, the outputs of which and the third output of the memory control unit are connected to the inputs of the OR element, the output of which is connected to the first inputs of the OR-NOT elements of the start channels, the second output of the first trigger 1 launch channel (J 1, t- - 1) is connected to the information input of the first trigger, with the first input of the second element I, with the second input of the first element NAND (j + 1) -ro of the launch channel and with the second input of the j-ro element And groups, the output of the first trigger (j + 1) -ro channel start up inn with the third input of the j-ro element AND group, the direct output of the second trigger of the triggered channel is the output of the trigger block, the first groups of information the inputs of the start delay selector and the restart feature selector are respectively connected to the bit outputs of the buffer register, the second groups of information inputs of the start delay selector and the restart feature selectors are the fourth and fifth groups of analyzer mode inputs, respectively, the combined selector clock inputs . Start Signs, Start Delay Signs Selector, and Restart Signs Selector are connected to the group of outputs of the synchronization pulse generator, the data inputs of the counters 0 are the inputs of the start-up delay setting and form the sixth group of inputs of the analyzer's mode, the fourth inputs of the AND elements of the group are the maximum resolution inputs 5 start delays of the start-up block and form the eighth group of inputs of the analyzer mode settings, in each Gth channel of the start-up block of the start block, the output of the first element I is connected to the second input of the OR0 element, whose output is connected to the installation input of the counter and the reset inputs of the second trigger and first trigger The direct output of which is connected to the second input of the second element AND to the third input of the first element NAND, the output of which is connected to the counting input of the counter, the output of which overflow is connected to the second input of the second element X -NON, the output of which is connected to the third input of the second element I, the output of which is connected to the installation input of the second trigger, the inverse output of which is connected to the third input of the first element I. 2. The analyzer according to claim 1, that is, so that the memory management unit contains a counter, a switch, four flip-flops and two pulse shapers, and the inverse output of the first pulse shaper is connected to inverse inputs 0 reset the first, second, third and fourth triggers, the inverse output of the second pulse shaper is connected to the inverse setting inputs of the first and third triggers, information 5, the first trigger input is connected to a logical zero bus, the inverse outputs of the first and second triggers are connected to the first group of information inputs of the switch, the first output of which is connected to the counting input of the counter and is the first the output of the block, the clock inputs of the first and second triggers and the first input of the second group of information inputs of the switch are combined to form the start input of the block, the inverse overflow output of the counter is connected to the second inverse reset input of the second trigger and the second input of the second group of information inputs of the switch, the second output of which is connected with the clock input of the fourth trigger, the information input of which is connected to the bus of the logical unit, the clock input of the switch is the clock input of the block, the enable input and the group of information inputs of the counter, the control input of the switch, the resolution inputs and the combined clock inputs of the first and second pulse drivers form the group of information inputs of the block, the group of bit outputs of the counter is with the first group of outputs of the block, the forward output of the second trigger, the group the bit outputs of the counter and the output of the fourth trigger form the second group of outputs of the block, the output of the third trigger connected to the information input of the second trigger, and the direct output of the first pulse shaper s are respectively the second and third unit outputs, 3. The analyzer according to claim 1, characterized in that the trigger feature selector contains an associative memory block, a multiplexer, a group of m multiplexers and a group of m elements AND, the first group of information inputs of the multiplexer forming the first group of information inputs of the selector, respectively combined the information inputs of the group multiplexers form a group of clock inputs of the selector, a group of address inputs, masking inputs and recording inputs, an associative memory block, a second group of information inputs and an address the multiplexer input, connected to the resolution input of the associative memory block, form the second group of information inputs of the selector, the multiplexer output group is connected to the group of information inputs of the associative memory block, the outputs of which are connected to the first inputs of the AND elements of the group, the second inputs of which are connected respectively to the outputs multiplexers groups, the outputs of the elements And groups form a group of outputs of the selector. 2c 29 30 L FIG 4