SU1732472A1 - Converter of binary code to modulo k code - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to build systems for the transmission and processing of discrete information. The aim of the invention is to reduce hardware costs. The binary code to modulo K converter contains a weight summation unit 1, a threshold unit 3, an output adder 4, and a convolution unit 2 of the discharge number. When the input code is fed at the outputs of the weight summation unit 1, a t 2g + 1-bit code is formed, the modulo K remainder is equal to the modulus K of the input code. The code from the outputs of block 1 is fed to the inputs of block 2 convolution of the number of bits that forms at its outputs log2 (K + 1) + 1-bit code, which is fed to the inputs of output adder 4 and the inputs of threshold block 3, which forms outputs, the deduction code is such that its summation with the code at the input of the first term of the output adder 4 gives, at its outputs, a residue code modulo K. 4 Il. (L С 1 сою и ю 01121

Description

The invention relates to automation and computer technology and can be used to convolve numbers by module.

The purpose of the invention is to reduce hardware costs.

FIG. 1 shows a 31-bit binary code converter circuit modulo K 11 code; in fig. 2 is a block diagram of a convolution number of bits for the case of K 11; in fig. 3 is a diagram of a 37-bit binary code converter into a modulo K 13 code; in fig. 4 is a block diagram of a convolution of the number of bits for case K 13.

The binary code to modulo K code converter contains a weight summation block 1, a convolution block 2 of the number of bits, a threshold block 3, an output adder 4.

The weight summing unit 1 is connected by inputs to the device inputs, and the outputs are connected to the inputs of the convolution unit 2 of the number of bits whose outputs are connected to the inputs of the threshold unit 3 connected by the outputs to the corresponding inputs of the second term of the output adder 4, the inputs of the first term of which are connected to the corresponding outputs block 2 convolution of the number of bits, and outputs - with the outputs of the converter.

The execution of weight weighting block 1 depends on the number of inputs and the task to be performed: convolution modulo K of a binary position code or count modulo K of the number of units of the input code. In general, it can be made as a set of full adders combined into levels, with the inputs of each of the first level adders connected to the converter inputs with weights ω for which (ft) mod K are the same, the inputs of each i-ro level adders connected to the outputs of adders of previous levels with weights with such that (co) mod K are the same, or with the outputs of adders of previous levels and inputs of the converter with weights that satisfy the specified condition. In the diagrams in FIG. 1 and 3 blocks 1 of weight summation 1 are made in the form of a set of complete adders of one level, because the number of inputs with the same values (a)) mod K is equal to three.

Weight weighting unit 1 converts the input code into a t 2r + 1-bit output code, where g is the power of the set of values of the residual weights of the bits of the input code modulo K in the case of forming the remainder of the input code modulo K, and g is the power of the set of values of the residuals the weights of bits of the natural binary code modulo K in the case of the formation of a residue

the number of units of the input code modulo K.

The convolution unit 2 of the number of bits is made as a group of series-connected adders (Fig. 2 and 4, for the cases K 11 and 13, respectively, where the number of adders is four). The inputs of the first adder are the inputs of the block, its outputs from the first to (g / 2) -th are connected to the inputs

the second adder (the first group of inputs of bits 1-g / 2, respectively), and the outputs from (g / 2 + 1) -th to g-th - with a group of inverse inputs of the second adder (from the first to i-ro, respectively). First transfer output

the adder, the outputs of the second adder and its inverse transfer output, as well as the outputs of any i-ro block adder are connected to the inputs of subsequent adders with weights, the sum of which is equal to the remainder modulo

To the weight of the output of the adder.

Unit 2 for the case of FIG. 2 contains 4 serially connected adders of binary numbers. In accordance with the described output, the sum Ss output of the second adder is connected to the inputs of the first and third bits of the fourth adder, since its weight is from 16, and (hell) mod K 4 2 ° + 22.

Block 2 converts the input t 2g + 1 bit code into the output I loga (К + 1) + 1-bit.

The threshold unit 3 contains a multithreshold element 5 with weights of inputs 2 (i О,

11 - 1) and exit thresholds А К, 2К, ..., К

and a residue shaping unit B, Multithreshold element 5 may be made as a. threshold elements, each of which contains series-connected elements AND, OR, and is performed as in a known converter. The unit 6 for the formation of deductions in the general case contains (a - 1) prohibition elements, where a is -

to

a m - the maximum code value at the inputs of the multi-threshold element 7, the outputs of which are connected to the inputs of the I elements OR. The j-th element of the ban is connected by inputs: direct - to the output of the multithreshold

element with a threshold j-K, and inverse - with the output of a multithreshold element with a threshold (j + 1) K. p is the element OR connected to the output of the p-th bit of the output adder 4, and the inputs to the outputs of the prohibition elements with numbers j for which in binary representation of the number Bj 2 - jK in

rm discharge there is one (,

 0). For the case shown in FIG. 1 and 3, the maximum value of j 2. In this case, the unit 6 for the formation of residues contains

one prohibition element, the direct input of which is connected to the output of the multithreshold logic element 7 with the threshold А К, and the inverse one with the output of the multithreshold element with the threshold А 2К.

Since for the case of K 11 (FIG. 1) W 5 and 62 10, the output of the inhibit element is connected to the inputs of the first and third bits of the adder 4, and the output of the multi-threshold element with the threshold А 2К - to the inputs of the second and fourth bits of the adder 4, the second group of inputs of which is connected to the output of the sum of the last adder of block 2. For case K 13 (Fig. 3) W 3 and Ba 6, while the output of the multithreshold element 7 with the threshold А К is connected to the second-bit input, the output of the projection element - with the input of the first digit, and the output of the multithreshold element with the threshold А 2К - with the input third bit yes adder 5

The operation of the inverter is as follows

When the input code converter is fed to the inputs, the output of the weight summing block 1 produces a t 2g + 1-bit code, the modulo K remainder is equal to the modulo K of the input code (the remainder of the input code modulo K), the code from the output of the block 1 enters the inputs of block 2 convolution of the number of bits that forms at its outputs I log2 (K + 1) + 1-bit code, the remainder modulo K is equal to the remainder modulo K code at the inputs of block 2 Code from the outputs of block 2 convolutions of the number of bits are fed to the inputs of the threshold block 3, and that as the inputs the output of the adder 4 (except the MSB), a second group of inputs of which is supplied with a threshold code output unit 3 such that the sum of the codes on the outputs of the adder 4 is equal to the sum of the residue of the input code (code number input unit) modulo K

Consider the operation of the proposed converter for the case depicted in FIGS. 3 and 4.

Let single signals are fed to the inputs Xi, Xs, Xb, Xg, Xi2. which corresponds to the code of the number X 2 ° + 22 +25 +28 +211 1 + 4 + 32 + 256 + 2048 2341, the modulo K 13 remainder is 1. At the same time, the single signals will be at the outputs of the sum of the first, third, sixth, virgins of the one and twelfth adders of block 1 weight summing, which are fed to the inputs of the first, third, sixth, ninth and twelfth bits of the first adder of block 2 of the convolution of the number of bits (Fig. 4), which causes single signals at its outputs of the sum Si, 83 Se, Sg, 812, which arrive on

the inputs of the second adder, causing a single signal at the output of the sum of Si and zero signals at the remaining outputs, while the single signals will be at the output of the sum

Si of the third and fourth adders of block 2 and zero signals are at its other outputs. A single signal from the output of the sum Si of the fourth adder of block 2 is fed to the input of the first bit of the output sum 0 of torus 4 and the input of the threshold block 3, but its outputs will have zero signals. In this case, the outputs of the adder 4 will be the code of the number 1, which corresponds to the remainder of the input code modulo K.

5 Thus, the proposed converter has lower hardware costs.

Claims (1)

Invention Binary Code to Code Converter 0 modulo K containing a weight summation block, a threshold block, an output adder and a convolution block of a number of bits containing a group of adders, the converter inputs of the converter being connected to the inputs of the corresponding bits of the weight summing unit, the outputs of which bits are connected respectively to the bit inputs The first term of the first addendum, the transfer entry and with the inputs of the second decimal part of the first adder of the convolution block group of the number of digits, the output of the total of the accumulator and the transfer output of the last adder of the block group convolutions of the number of bits are connected respectively 5 with the inputs of the bits of the threshold block, the outputs of the bits of the sum., The last adder of the group of the convolution block of the number of bits are connected to the inputs of the corresponding bits of the first term of the output adder, The 0 bits of the sum of bits are the outputs of the bits of the converter, the outputs of the bits of the threshold block are connected to the inputs of the corresponding bits of the second term of the output adder, outputs of the bits from the first through f / 2 (r is the power of the set of values, residuals of the input code modulo K) the sums of the first adder of the group of the convolution block of bits are connected to the direct inputs of the corresponding 0 bits of the first term of the second adder of the convolution block group of the number of bits, outputs with weight W of transfers of each adder, except the second and last, group and outputs with weight W of digits of the sum5 of each adder, except the first and last, group of convolution unit of the number of bits The ports are connected to the inputs of the bits with weights corresponding to the single binary code values of the modulus W mod K of the terms of the subsequent adders of the group of the convolution block of the number of bits, characterized in that, in order to reduce hardware costs, the outputs of bits c (g / 2 + by the r-th sum of the first adder of the convolution block group of the number of bits are connected respectively to the inverse inputs of the second term of the second adder of the convolution block group of the number of bits, the transfer input and the inverse transfer output of the second adder of the convolution block group of the number of bits are connected respectively to the input the logical unit of the converter and with the input of the unit of the unit weight of the summand of the subsequent summatr of the convolution block group of the number of bits. FIG. g 3 55