SU1732292A1 - Digital impedance meter - Google Patents

Abstract

The invention relates to a measurement technique and is intended for measuring parameters of radio radio stations. The purpose of the invention — improved performance and enhanced functionality — is provided by reducing the time to

Description

The invention relates to a measurement technique and is intended for measuring parameters of an electric radio circuit: components of impedance and admittance, capacitance and its loss tangent, inductance and its quality factor.

The purpose of the invention is to increase the speed and expansion of the application range by measuring the impedances and conductivity and determining the frequency characteristics of the circuit under study.

Fig. 1 shows a block diagram of a digital impedance parameter meter; Fig. 2 is a block diagram of the control unit; FIG. 3 shows temporary digrams explaining the principle of operation of a digital meter.

The digital impedance parameter meter contains a sinusoidal voltage generator 1, a resistance-voltage converter 2, a rectifier 3, a voltage-to-frequency converter 4, a control unit 5, elements 6-11, reversible counters 1-15, counters 16 and I7f converter 18 periods per code

selectors-multiplexers 19 and 20, counter 21 addresses, encoders 22-24, decoder 25, divider 26 codes, memory register 27, delay element 28, demultiplexer 29, trans- (. multiplier 30 codes, calculation block 31, registration block 32 , input terminals 33 and 34 and the studied radio radio 35.

The output of the sinusoidal voltage generator 1 is connected to the first input of the control unit 5 and the signal input of the converter 2 resistance - voltage, the measurement inputs of which are connected to the input terminals (or terminals) 33 and 34, to which the circuit under study 35 is connected. - the voltage is connected to the second input of the control unit 5, to the first output of which through the rectifier 3 is connected the input of the voltage converter 4 to the frequency, the output of which is connected to the first inputs of the elements AND 6 - 1 G, sec Their inputs are connected, respectively, to the second, third, fourth, fifth, sixth and seventh outputs of control unit 5. The outputs of the elements And 6 - 11 are connected

with counting inputs of reversible counters 12-15 and counters 16 and 17, respectively, the reverse inputs of reverse meters 12 and 15 are connected to the eighth output of control unit 5, the reverse inputs are reverse of counters 13 and connected to the ninth output of control unit 5. The information output of the reversible counter 12 is connected to the first information inputs of the selector multiplexers 19 and 20, the information outputs of the reversible counters 13 and 14 are connected to the fifth and sixth information inputs of the selector multiplexer 19, the information output of the reversible counter 15 is connected to the second information inputs of the selectors multiplexers 19 and 20, the information output of the counter 16 is connected to the third information inputs, and the information output of the counter 17 to the fourth information inputs of the selectors The multiplexers 19 and 20. The input of the period converter 18 to the code is connected to the tenth output of the control unit 5, and the output is connected to the seventh information input of the selector-multiplexer 19, the right information input of the selector-multiplexer 20 and the first input of the multiplier 30 of codes. The outputs of the multiplexer selectors 19 and 20 are connected to the first and second inputs of a code divider 26, the output of which is connected to the information input of memory register 27, the synchronization input (record) of which is connected to the input of the address counter 21 via the delay element 28 and the eleventh output of unit 5 control, and the output is connected to the second input of the registration unit 32 and the information input of the demultiplexer 29. The output of the address counter 21 through the encoders 22 - 2k is connected to the address inputs of the multiplexer selectors 19 and 20 and the demultiplexer 29, respectively via the decoder 25 to the enabling inputs of the multiplexer selectors 20 and 19. The second input of the decoder 25 is connected to the fourth input (sign input) of the registration unit 32 and to the sign output of the reversing counter 12. The first output of the demultiplexer 29 is connected to the sixth information input of the selector - multiplexer 20; the second output - with the second input of the multiplier 30 codes, the third output - with

the input of the calculation unit 31, and the outputs of the multiplier 30 codes and the calculator 31 are connected respectively to the first and third inputs of the registration unit 5 32.

Control unit 5 (Fig. 2) contains null-bodies 36-39, discriminators 40 and 41 maxima, triggers 0 42-54, two-input elements And, generator 65 clock pulses, counter 66 clocks, elements 67 and 68 delays, driver 69 pulses , element OR 70, button 71 and Start, switch 72 Mode of operation, analog key 73.

The first input (V.1) of the control unit 5 is connected to the first input of the analog switch 73, the inputs of the zero-Q organs 36 and 37 and the input of the discriminator 40 maxima. The second input (V.2) of the control unit 5 is connected to the second input of the analog key 73, the inputs of the zero-organs 38 and 39, and the input of the maximum 41 discriminator. The zero-organ output 36 is connected to the S-input of the trigger 42, the S-input of the trigger 47, the S-input of the trigger 48, the counting input of the trigger 49 and the second inputs of the elements 62 and 63. The output 0 of the zero-organ 37 is connected to the R-inputs of the triggers 42 and 43. The output of the discriminator 40 highs is connected to the R-input of the trigger 44 and S-input of the trigger 46, the output of the zero-body 38 is connected to the S-inputs of the trigger 43 - 45. The output of the zero-body 39 is connected to the R-inputs flip-flops 43 and 45. The discriminator output 41 of the maxima is connected to R-inputs 46 and 47. The direct outputs of the flip-flops of the flip-flops 44 - 49 are connected, respectively, to the second input element TA and 55 to the second input of AND gate 56, to the second inputs of AND gates 57 and 58, to the second inputs of the AND elements 5 comrade 59-61. The first inputs of the elements And 55, 57, 60 and 61 and the control input of the analog switch 73 are connected to the forward output of the trigger 50. The first inputs of the elements 56, 58 and 59 0 are connected to the direct output of the trigger 51. The inverse output of the trigger 50 is connected to R-input trigger 52 and through the element 68 delay with S-input trigger 53. Inverse output 5 trigger 51 is connected to the R input of the trigger 53 and to the S input of the trigger 54. The counting inputs of the trigger 50 and 51 are connected to the outputs of the elements And - 62 and 6; accordingly, the first inputs of which are connected to the direct outputs of the triggers 52 and 53. The direct output of the trigger 5 is connected to the first input of the AND 6A element, the second input of which is connected to the output of the generator 65 clock pulses. The output element And 64 is connected to the input of the counter 66 clocks, the output of which is connected to the R-input of the trigger 5 and the movable contact of the switch 72, the S-input of the trigger 52 is connected to the output of the element OR 70, the first input of which is connected to the output of the driver 69, the second input - to the output of the element 67 delay and the third input to the input of the device External start. The input of Impulse Shaper 69 is connected to the Start button 71, and the input of the delay element 6 is connected to the second fixed contact of the switch 72, the first fixed contact of which is open.

The output of the analog switch 73 is the first output (V.1) of control unit 5, the direct outputs of the flip-flops 42 and 43 serve as the eighth (V.8) and ninth (V.9) outputs, respectively, and the outputs of the And 55, 56 elements , 57, 58, 59, 60, 61 and 64 are respectively fifth (Out. 5), sixth (Out. 6), second (Out. 2), fifth, (Out, 5), third (Out. C) , the seventh (Out.7), tenth (Out.10) and eleventh (Out 11) outputs of the control unit 5.

The digital impedance parameter meter operates as follows.

From the output of the generator 1, a sinusoidal voltage U (t) is applied to the signal input of the resistance-to-voltage converter 2 and the first input of the control unit 5. Let the voltage U (t) and the current i (t) in the converter circuit 2, the resistance to voltage be described by the expressions:

U (t) Um-sinCOt; i (t) Im sin (cot - Cf),

(12)

U, lm - voltage amplitudes

U (t) and current i (t), respectively;

C is the phase shift between voltage and current, equal to the argument of the impedance complex Z;

CO is the circular frequency of voltage and current.

The initial phase of the voltage U (t) is taken to be equal to zero for simplicity, records, which does not change the substance of the subsequent analytical relations.

Usually, the current i (t) is transformed into a proportional voltage Uj (t) on the model resistance RO connected in series with the resistance Z of the circuit under study:

U; (t) U; no. sin (COt-Cf), where U; R I L ° Um

(3)

amplitude

ij

 voltage on the model

RO resistance. The voltage U- (t) from the output of the voltage converter 2 to the resistance is fed to the second input of the control unit 5,

In the initial state, the first output of the control unit 5 to the rectifier 3 is supplied with the voltage U (t), and from the output of the rectifier 3 the module of this voltage (u (t) | enters the input of the voltage converter k to the frequency, wherein the voltage ju (t) l is converted into a proportional pulse frequency

f (t) K (U (t) j,

where K .j is the transfer coefficient (or conversion) of converter 4

voltage to frequency. All elements 6-11 are closed at their second inputs by control signals from the second, third, fourth, fifth, sixth and seventh respectively.

the outputs of the control unit 5, the reversible counters 12-15, the counters 16 and 17 and the address counter 21 are reset. In the control unit 5, the time moments t0, t and t are allocated, ts

transition voltage U (t),)

through zero values from the negative to the positive region and vice versa, as well as the time moments tz, t3 of the voltage transitions U (t), U- (t)

through positive peaks (fig.Z). Through these transitions, six control signals are formed, the duration of which (tЈ-t,), (ty-t,), () ,. (t3-to), (t4-t0), (t6-t0).

K

However, they do not arrive at the outputs of control unit 5. In addition, in control unit 5, two control signals are formed, each of which is

It contains information about the polarity of the measuring signals U (t) and U; (t) or i (t). The first of the specified polarity control signals is supplied via the eighth output of the control unit 5 to the interconnected inputs of the reverse of the reversible counters 12 and 15, and the second control signal of the reverse is fed through the ninth output of the control unit 5 to the interconnected inputs of the reverse of the reversible counters 13 and 1. They serve to set the counting modes of the input pulses of reversible counters 12, 15 and 13, l depending on the polarity of the signals U (t) and U; (t) respectively

The control unit 5 can operate in two modes: manual and automatic, which are set by the switch 72 Operating mode. An external trigger is also provided, for which there is an input of the same name.

Consider the operation of the control unit 5 in the manual mode (or the one-time measurement mode from the Start button 71), in which the switch 72 is set to the Manual position.

In the initial state, in which the device is installed when it is turned on, the reversible counters 12-15, the counters 16 and 17, the counter 21, the memory register 27 are wrapped, and in the control unit 5 all the triggers are set to zero. the low level signal from the direct output of the trigger 50 is closed at the first input elements And 55, 57 60, 61, and the analog switch 35 is open at the second input, the low level signal from the direct output of the trigger 51 are closed at the first input elements And 56, 58, 59, the low level signal from the direct output of the trigger 54 is closed by ne To the left input element AND 64, The outputs of the elements 55, 56, 57, 58, 59, 60, 61 and 64 form prohibitive signals of a low level, which are fed to the corresponding outputs of the control unit 5.

The pulses from the output of the zero-body 36, formed at the times t0, tg, t .. (FIG. 2), go to the S-inputs of the flip-flops 42, 47 and 48, to the counting input of the flip-flop 49 and to the second inputs of the elements And 62 and 63 through which the pulses do not pass, since these elements are closed at the first entrance. The pulses from the output of the zero-body 37, formed at time points

ten

15

20

25

3229210

t (Q, ",., are applied to the R inputs of the flip-flops 42 and 48, The pulses from the discriminator output 40 maxima generated at times t, to, ..., are sent to the R-input of the trigger 4 hours and to the S input trigger 46. The pulses from the output of the null organ 38, generated at times t, t7, ..., arrive at the S-inputs of the flip-flops 43-45, and the pulses from the exit of the null organ 39, generated at times t, t s , to the R-inputs of the flip-flops 43 and h5, and the pulses from the output of the discriminator 41 pulses generated at the times t, to, ..., to the R-inputs of the flip-flops 46 and 47.

The triggers 42 and 43 switch every half-period of the voltages U (t) and U; (t), respectively, therefore the signals at the direct outputs of these triggers carry information about the polarity of the voltages U (t), Uj (t). At the direct outputs of the flip-flops 44 - 49, control signals are generated whose durations are (), (), (tj-ta), (tytg), (t4-t0) and (t6-t0), respectively. These signals are sent to the second inputs of the And 55 - 61 elements, respectively, but they do not pass to their outputs, and consequently, to the corresponding outputs of the control unit 5, since the indicated And elements are closed at the first input by low level signals from 35 moves of triggers 50 and 51.

The device is transferred to the measurement mode by pressing the Start button 71. At the same time, a pulse is generated at the output of the pulse shaper 69, which through the OR element 70 is fed to the reset bus and to the S input of the trigger 52. It is not shown on the reset bus signal , in order not to obscure them by obvious connections, the signal confirms the initial state of the instrument. The operation of a digital measuring instrument for impedance parameters can be divided into two stages: at the first stage, primary or 50 interim results are obtained in the form of codes and memorized; at the second stage, measured values are determined by intermediate results, i.e. This step is computational. In turn, the first stage of measurement is carried out in two cycles.

The measurement process, its first stage, starts at the Start 30 signal.

either formed in control unit 5, or supplied to it from an external source. The first measurement cycle begins.

In block 5, the control signal is removed for the following four control signals to pass: duration () at the second output, duration (tg-t0) at the third output, duration (,) at the sixth, and duration () at the eighth output of control block 5. These signals are respectively transmitted to the second input of the element 6, to the input of the converter 18 of the period to the code, to the second input of the element 9 and to the second input of the element 11. The elements 6 and 9 and 11 are opened for a time determined by the duration each of them is control signals, and the counting inputs of the reversible counters 12, 15 and counter 17 receive pulses of the frequency f (t) from the output of the voltage-frequency converter 4. The mode of operation of the reversible counters (12 and 15) (summation or subtraction and polarity dependence of the voltage U (t) is set by the control signal from the ninth output of the control unit 5. The counter 17 is accumulated (or summed), because its integration or counting time () corresponds to the positive half-wave of the voltage U (t),

During the open state of the elements AND 6, 9, 11, the counters 12, 15, and 17 will record the numerical values determined by the known relations (4), (5), (6) shown in Table 1.

In the period converter 18, the period code NT is generated, which, like in a known meter, is produced by a known sequential counting method, i.e. filling the time interval proportional to the period, in this case equal to the period tg-t0 T, with pulses of exemplary frequency. The period code is determined by the equality

mt ct

t,

where CT is the transfer coefficient of the converter 18 period in the code,

This completes the first clock t of the meter and it goes

0

five

0

five

0

five

to the second clock cycle. For this, the control unit 5 commits the measuring signals and sends the voltage U; t to the first output of the rectifier 3, and the voltage fj from the output of the voltage converter 4. (t) is proportional to the voltage {U, (t) /.

In control unit 5, the prohibition on passing control signals by its second, tenth, and seventh outputs is restored and the prohibition on passing control signals is reduced: on the third output (ta, -t0), on the fourth output (ta -t.2.) and on the sixth output with a duration () These signals are fed to the second inputs of elements AND 7, 8 and 10, respectively, opening them for the passage of frequency pulses fj (t) from the output of the voltage-to-frequency converter 4 to the counting inputs of reversing counters 13 and 14 and counter 16, respectively, in which, during the open state of the elements And 7, 8, and 10, the numerical values determined by the known expressions (7), (8) and (9) shown in Table 1 will be written.

This completes the second cycle, and consequently, the first stage of measurements — obtaining intermediate results NXA, N

N

91

N

Rl

NRi Ny2,

32. L and T The meter proceeds to the second stage of measurement - the determination of the measured values from 0 intermediate results obtained in the first stage. The calculation formulas for determining the measured values are given in Table 2.

The measured value and its calculation algorithm are specified by the address of the measured value using the address counter 21, the encoder 22-2k and the decoder 25. To do this, from the control unit 5, the eleventh output to the address counter 21 of the address is given a clock pulse of a predetermined frequency determined by speed performing computational operations. With the arrival of each clock pulse, the status of the address counter 21 is changed by one, and its output code is assigned through the encoders 22-24.

13

selectors-multiplexers 19 and 20 of the switching output code of memory register 2 to the fifth input of the selector-multiplexer 20 and to the inputs of the multiplier 30 codes and block 31 (calculation (calculator of the iarctg function). For example, when recording the first clock pulse in the estimator 21 addresses (first address) determines the active resistance R of the impedance Z. In this case, the selectors multiplexers 19 and 20 are set to the address inputs by signals from the outputs of the encoders 22 and 23 in such states that the output selector-multiplex Lexor 19 at its second input is fed the code Nj from the information output of the reversible counter 15, and the output of the selector-multiplexer 20 through its third input receives the code N R2 from the information output of the counter 16. The code NR from the output of the selector-multiplexer 1 is fed to the first input ( the input of the divisor) divider is 26 codes, and the code from the output of selector-multiplexer 2 is at its second input (divider input). At the output of the code divider 26, an NR code of resistance R is formed. This code is written to the memory register 27 by a clock pulse arriving at its synchronizinginput (record input) from the eleventh output of control unit 5 through delay element 28, the delay time of which is set somewhat longer than the calculation time in code divider 26 The code from memory register 27 goes to the registration unit and to the information input of demultiplexer 29,

In this way, all measurable quantities associated with the division of two intermediate quantities are determined. These values are: active R, reactive X and total Z resistance; active p, reactive b and full Y conduction, the quality of the inductor; loss tangent tg & a capacitor; amplitude

The voltage Uzrn at the output of the circuit Z under study. The algorithms for determining the inductance of capacitance C and phase shift C are somewhat different from this. Consider each one of them,

II

The values of L and C are found from the reactive resistance X taking into account its x- | Ractera (inductive or capacitive),

0

0

five

292

U

which is determined by the sign of X (plus or minus, respectively). To set the measured quantity L or С, the signal from the sign output of the reversible counter 12, in which the code of the value X is formed, is fed to the second input of the decoder 25 and the sign input of the registration unit 32. The decoder 25 serves to set the inhibit signal to the enable inputs of the selector multiplexers 19 and 20 in the following four modes: when calculating the values of C and tf $, if

j (fourth and ninth address), when calculating the values of L and Q, if X O (third and tenth address). Thus, only one pair of quantities is measured: either T, and Q, or C and tp8, and the measurement mode of another pair of quantities is prohibited: either C and tg $, or L and Q, When determining all other values, multiplexer selectors 19 and 20 open permits entry.

Since the values of L and C are calculated from the reactive resistance X, it is rational to find them after determining the value of X (second address). In this case, the Ny code of X will be written in memory register 27.

When measuring inductance L

(third address) after entering

The counter of the address of the third clock pulse, a signal from the output of the encoder 2, is fed to the address input of the demultiplexer 29, the latter opens on the second output, and the Px code from the output of the memory register 27 goes to the second input of the multiplier 30 codes, the first input of which is supplied NT code of period T from converter output 18 period - code. Then, at the exit, the varnum 30

5 codes, inductance code N 1.4 is generated. The NL code is fed to the second input of registration unit 32.

0

0

When measuring the capacitance C (the fourth address) after the fourth clock pulse address arrives at the counter 21 by the signal from the output of the encoder 2, the demultiplexer 29 opens at the first output. The Nx code from the memory register 27 goes through it and through the selector-multiplexer 20, through the fifth open input, to the second input of the divider 26 codes, to the first input of which the NT code is fed from

151732292

Former 18 period - the code through the selector-multiplexer 19, according to its seventh open INPUT. At the exit de; Code number 26 is formed. N / capacity code C.

| t

When measuring the phase shift (the twelfth address), the selector-multiplexer 19 is open at the first input and its output receives a code from the information output of the reversible counter 12, and the selector-multiplexer 20 is open at the second input and its output receives the code N $, from the information output reversible counter 15. The output divider 26 codes

 Nv "

the code is Ndop, which

in the HCH, R is written to memory register 27.

In this mode, the lemultiplexer 29 is opened by a signal from the encoder 2k on the third output, and the N-tgqj code from the output of the memory register 27 is input to the arctg function calculation unit 31, the output of which is the Nq arctg code M.c $ C {supplied to the third input of the block 32 registration,

When determining the frequency characteristics of the examined circuit Z, the values of U / zrn and cp are measured in the required frequency range of the measuring signal U (t) at the output of generator 1, whose frequency can be tuned either manually or programmatically

By reducing the time to obtain intermediate values, the speed of the digital impedance parameter meter is improved. Enabling the measurement of additional parameters and frequency characteristics — amplitude-frequency and phase-frequency — expands the range of application of the digital impedance parameter meter.

Claims (1)

Invention Formula A digital impedance parameter meter containing a series-connected sinusoidal voltage generator and a resistance-voltage converter, a voltage-frequency converter, a period-code converter, a code divider, a serially connected code multiplier and a registration unit, a first selector-multiplexer and a control unit 16 0 five 0 five 0 five 0 S 0 five voltage and converter resistance - the voltage is connected to the first and second inputs of the control unit, characterized in that, in order to increase the speed of measurements and expand the range of application by measuring the impedance and conductivity and determine the frequency characteristics of the circuit under study, it is additionally introduced the rectifier, the input of which is connected to the first output of the control unit, and the output - to the input of the voltage converter - frequency, six elements And, four reversible counters and two sensor, second selector-multiplexer, address counter, three encoders, decoder, memory register, demultiplexer, calculator and delay element, the first inputs of the first, second, third, fourth, fifth and sixth And elements are connected to the output of the converter frequency, the second inputs of these elements And are connected respectively to the second, third, fourth, fifth, sixth and seventh outputs of the control unit, and the outputs of the first, second, third, fourth, fifth and sixth elements And are connected to the counting inputs of the corresponding First, second, third and fourth reversible counters, first and second counters, the reverse inputs of the first and fourth reversible counters are connected to the eighth output of the control unit, the reverse inputs of the second and third reversible counters are connected to the ninth output of the control unit. connected to the first information inputs of the selectors-multiplexers, the information output of the fourth reversible counter is connected to the second information inputs of the selector in multiplexers, information outputs of the first and second counters are connected respectively to the third and fourth information inputs of multiplexers selectors, information outputs of the second and third reversible counters are connected respectively to the fifth and sixth information inputs of the first selector multiplexer, seventh information input of the first selector multiplexer and fifth infor171 The mapping input of the second selector-multiplexer is connected to the first input of the code multiplier and with the output of the period converter - the code whose input is connected to the tenth output of the control unit, the output of the first selector-multiplexer is connected to the first input of the code splitter, the second input of which is connected to the output of the second selector - multiplexer, the sixth information input of which is connected to the first output of the multiplexer, the output of the code divider is connected to the information input of the memory register, the synchronization input of which is Through the delay element is connected to the eleventh output of the control unit and the input of the address counter, 3229218 the output of which is connected via the first, second and third encoders to the address inputs of the second, first multiplexer and demultiplexer, respectively, and through the decoder to the enabling inputs of the multiplexer selectors, the information input of the demultiplexer is connected to the second input of the block and the memory register output, The second and third outputs of the demultiplexer are connected respectively to the second input of the code multiplier and the input of the computation unit, the output of which is connected to the third input of the registration unit, the fourth input Which is connected to the second input of the decoder and to the sign output of the first reversible counter. to 15 Table 1 Counter readings KilHBL.einq, (4) .costf (5) N | ftoЈiJb. (6) 5i btfЈa.coecf (7) KillsUKS-.pin q, (8) NX2 SillslSo (9) nineteen 1732292 N Rl Net NR N KZ-R to 1 / 2R0 20 Table 2 one Out f W / x.9 A Bb / x.W 'Вш.9 A //; w „rH 72 q 0 & ct / HpaSowF 1.8 external ABtrJ. launch Rig.2 t / HpaSo Rig.2