SU1718133A1 - Relative voltage alteration meter - Google Patents

Abstract

The invention relates to a measurement technique and can be used in measuring dielectric characteristics. The purpose of the invention is to expand the measurement range, which is achieved by using two logical elements OR 8, 9, D-flip-flop 7, key 6 due to the choice of the number of bits of counters, taking into account the required accuracy and the number of T-flip-flops, taking into account the range of the measured voltage . The device also contains a voltage converter 1 - frequency, two keys 4.5, a reversible counter 2, a counter 3, a digital recording unit 11, a delay element 12, a control unit 10. 1 hp f-ly, 3 ill.

Description

1

The invention relates to a measurement technique and can be used in loss measurement units in dielectric analyzers.

A device for measuring voltage changes, implemented in a diesel meter, contains an analog unit for calculating the ratio of two voltages, a memory device and a subtractor.

The device works as follows.

The Do voltage is stored in the memory. The output of the storage device is connected to the first input of the subtractor, the second input of which is supplied with the voltage Ux (Ux Uo). The difference (Do - Ux) of the voltages from the subtractor is fed to the first input of the unit for calculating the ratio of two voltages, the second input of which is supplied by the voltage Ux. At the output of the unit for calculating the ratio of two voltages, the result is a voltage Uo-Ux

relation equal to the relation

their

proportional to the measured conductivity QX, equivalent to the dielectric loss in the sample under study.

The voltages U0 and Ux are fed to the input of the device periodically from the same source, therefore a memory device is needed, the input of which is connected to the source through a switch synchronized with the appearance of voltages Uo and Ox.

The main disadvantage of this device is its low accuracy. Sources of error are leaks in the insulation resistance of the analog memory device and the switching key. Low accuracy is generally inherent in devices that use information processing in analog form.

Closest to the present invention is a device for measuring the relative increments of analog signals, intended for use in an automatic diesel meter.

The device contains an ADC that converts the input signal level into a number of pulses, two reversible counters, a counter, two keys, a delay element, a control unit, and a digital recording unit. The device allows you to automatically determine the relative imputation of the descending signal to its original level.

The ADC output through the first key is connected with the direct count input of the first binary decimal counter, the transfer output (overflow) of which is connected with the direct count inputs of the second reversible counter and counter, whose information outputs are connected to the inputs Set the second reverse account, transfer output which - through the delay element with the inputs of the countdown of the first binary-decimal reversible counter and the preliminary recording of the second reversible counter, the countdown input of which is connected to the output via a second key one ADC, with the outputs of the control unit connected to the control inputs of the keys, the Reset inputs of the counter and the second reversible counter, and the Reset input of the first reversing counter; information outputs of which are connected to the inputs of the digital registration unit.

The device works as follows.

Presetting the counters to zero, the control device opens the key, and the ADC pulses enter the direct count input of the first binary-decimal reversing counter, acting as a frequency divider with the number of decimal digits k. 1/1 overflow pulses of the first reversible counter to the input of the counter and. input direct account of the second reversible counter.

The number of counter bits is determined by the required measurement accuracy. For example, if the calculation error should be no higher than 1%, then the first binary-decimal reversible counter should have at least two decimal places (k -2), and the capacity of the second reversible and non-reversible counters should allow to write the corresponding first transformable value live number

M E () 100,

where In - the number of pulses that passed through the first key;

R

Ј - the whole part of the relationship-t.

The time of the analog-digital converter of the input signal, i.e. the time at which the keys are opened is chosen so that the second reversible counter is as full as possible, but at the same time not overflowed.

Then, the control unit, having previously set the first reversible counter to zero, which corresponds to the entry in it of the number 10k (100 when k 2), opens the second key, through which the ADC pulses corresponding to the smaller of the transformed voltages arrive at the input of the reverse

bills of the second reversible counter and subtracted from its contents. When the second reversible counter is set to zero, a signal appears at its output, is fed to the countdown input of the first reversible counter and to the pre-recording input of the second reversible counter. As a result, a parallel rewrite of the contents of the non-reversible counter into the second reversible counter takes place.

Thus, in the second part of the measurements, the second reversible counter with respect to the first reversing counter performs the role of a frequency divider with a division factor N. The total number of overflow pulses received when the second reversing counter is counted down is

Ri-E (§)

where Bi is the number of pulses passed through the second key, corresponding to the numerical equivalent of the second voltage U (ti);

cV |

E is a whole part of the number - yy.

Therefore, after the end of the measurement cycle, the contents of the counter will be equal to

gi 100k-ri.

that for k 2, with an accuracy of 1%, corresponds to the true value of the relative increment of the signal at the input of the ADC, which is determined by the formula

q.-p (toU-and ft). iop

9U (to)

where U (t) is the signal under study;

to ti are the instants of time with respect to which the magnitude of the change in the signal is estimated.

The measurement result is displayed using a digital recording unit.

The disadvantages of the known device for measuring the relative change in the analog signal are its complexity (it is necessary to use two reversible counters), the impossibility of using it in resonant dielectric parameter meters and an admittance meter in which the relative voltage change on the LC circuit is to be measured. after inserting the test substance into the capacitive sensor included in the resonant circuit. In this case, the calculation should be carried out according to the formula

 Uo-Ux m

 .9k

where QX is constant,

UD is the voltage on the circuit prior to the introduction of the test substance;

Ux is the voltage on the circuit after the substance is introduced into the cell (Ux Uo, i.e., it is necessary to calculate the ratio of the absolute change in voltage to the smaller of 5 voltages).

The purpose of the invention is to simplify the device for measuring the relative voltage variation while at the same time making it possible to use it as a digital unit for measuring the dielectric losses in resonant conductors and extending the measurement range.

The goal is achieved by the fact that

5, a device containing a voltage to frequency converter, two keys, a reversible counter, the direct count input of which is connected to the output of a voltage to frequency converter through a first key, and a second

0 a counter, a digital recording unit, a delay element and a control unit, the first two outputs of which are connected to the control inputs of the first and second keys, additionally introduced two OR circuits, D5 trigger and connected between the third clock output of the control unit and the counting input of the second counter third key whose control input and the first input of the first OR circuit are connected to the output

0 D-flip-flop, the synchronization input of which and the second input of the first OR circuit - with the second output, the control unit, the fourth output of which is connected to the inputs of the installation of zero counters and the first input of the second

5 of the OR circuit, the second input of which is connected to the reverse transfer output of the first reversible counter, the counting input of which is connected to the output of the voltage-frequency converter through the second

0 key, the control input of which is connected to the output of the first OR circuit, and the output of the second OR circuit to the reset input of the D-flip-flop, the output of which is connected to the input through the delay element Record of the digital display unit, whose information inputs are connected to the corresponding outputs second counter.

The control unit of the device is made in the form of two M-input circuits AND, forming the bodies of a reset pulse, whose input is connected to the output of the first AND circuit, and series-connected clock generator and M T-flip-flops, with the first output of the control block including the output of the first circuit And, the inputs of which are connected to the direct outputs of the first M-1 T-flip-flops and the inverse output of the last T-flip-flop, the direct output of which is connected to the input of the second And circuit, the remaining inputs of which are connected to

the inverse outputs of the remaining T-triggers, the output of the second circuit I is the second output of the control unit, the third output of which is the additional output of the clock pulse generator, and the number of M T-triggers is determined by the formula

M. .ichmin

where is the whole part of the number x;

Uo is the maximum voltage value at the input of the device, relative to which voltage variations are measured;

Ux min is the minimum voltage value at the device input.

FIG. 1 is a schematic diagram of an apparatus for measuring relative stress variation; in fig. 2 is the basic scheme of the control unit; in fig. 3 - time diagrams of voltages that explain the operation of the device: a - at the output of the clock generator; V-e - on direct outputs of T-flip-flops; f - at the first output of the control unit - signal, which opens the input of the direct account of the reversible counter; d- at the second output of the control unit; h - at the output of the D-flip-flop - at the control input of the second key; I is at the control input of the first key opening the PC2 countdown input.

 The device contains an input voltage-to-frequency (IFF) converter 1, a reversible counter, a counter 3, keys 4-6, a D-flip-flop 7, an OR circuit 8-9, a control unit 10, a digital registration unit 11, and a delay element 12.

The forward and reverse counting inputs of the reversible counter 2 with the output of NLF-1 are connected respectively via keys 4 and 5, the control inputs of which are respectively connected to the first output of the control unit 10 and the output of the OR 8 circuit.

The reverse transfer output of the reversible counter 2 is connected via the OR circuit 9 to the reset input of the D-flip-flop 7, the synchronization input of which and the first input are OR8 8 connected to the second output of the control unit 10, the third clock output of which is connected to the counting input of the counter 3 via the key 6. The fourth output of the control unit 10 is connected to the inputs for setting the meters to zero and the second input of the OR circuit 9. The output of the D-flip-flop 7 is connected to the control input of the key 6, the second input of the OR circuit 8 and through the delay element 12 to the input of the block 11 digital register tion, whose data inputs are connected to respective outputs of the counter 3.

The control unit 10 comprises two four-input circuits AND 13 and 14, a shaper 15 of reset pulses, the input of which is connected to the output of the AND circuit 13, and a series-connected generator of 16 clock pulses and T-flip-flops 17-20. The first output of the control unit is an output of an AND 13 circuit, whose inputs are connected to direct outputs of T-flip-flops 17-19 and an inverse output of T-flip-flop 20, a direct output of which is connected to an input of AND circuit 14, which other inputs are connected to inverse outputs T-flip-flops 17-19. The second output of the control unit is the output of the circuit 14, the third output is the additional output of the generator 16 clock pulses, the fourth the output of the driver 15 reset pulses.

At time ti, unit 15, by a positive voltage drop arriving at its input from the output of the circuit 13, generates a short (about 75 ns) pulse at the output that from output 3 of block 10 enters the inputs Cleaning of counters 2 and 3 and

through the scheme OR 9 to the reset input of the D-trigger 7.

At the same time, a high level of voltage from the output AND 13 (output 1 of the control unit 10) to the control

the input of the key 4, opens the entrance of the direct account of the reversible counter 2.

During the period from ti to ta, the reversible counter 2 is filled from the direct counting input with pulses whose frequency is proportional to the reference voltage Uo.

The duration is determined by the time in the single state of the trigger T 17.

At time t2, a voltage source (Ux Uo) is connected to the input voltage-frequency converter 1. At the same time, the output of block 1 switches from the direct count input to the countdown input of the reversible counter 2. The output of block 1 is connected to the countdown input of the reversible counter 2 by key 5, to the control input of which through the OR 8 circuit since time t2 no ta enters a high

voltage level from output 2 of control block 10 (output of circuit 14).

At time point I, the falling edge of the voltage from the output of the circuit AND 14, D-flip-flop 7 is set to one and

a high level of voltage from its output, entering through the circuit OR 8 on the key AND 5, leaves open the countdown input of the reversible counter 2 and, entering the control input of the key KB, allows

pulses from the clock generator 16 to the counter 3.

Thus, in the time interval from ti to t2, the reversible counter 2 is filled from the direct count input with pulses whose tracking frequency is proportional to Uo, and since t2 from the counting input with pulses whose tracking frequency is proportional to Ux (Ux U0).

Therefore, since t2 - ti ° ta -12, by the time ts in counter 2, the number of pulses will remain recorded, which is proportional to the difference in voltage U0 - Ux. From this point in time (r3) the counter begins to be filled with 3 pulses from the generator of 16 clock pulses. The filling of the counter 3 continues until the contents of the reversible counter 2 passes through zero, while the output of the reversing counter 2 is accompanied by a reverse transfer pulse coming through the OR 9 circuit to the Reset input D-flip-flop 7, and a low voltage level at its output it disables the input of the counter 3 from the output of the clock generator.

Obviously, the time () of filling the counter 3 is directly proportional to the voltage difference () the number of pulses remaining in the reversible counter 2 by the time point ta, and inversely proportional to the voltage Ux (inversely proportional to the pulse frequency input to the reverse counting input of the reverse counter 2 i.e.

“. Uo-Ux m

9k-DT N9 where the proportionality coefficient;

Ng is the number of pulses recorded by counter 3 at time t4.

Determine how the proportionality coefficient is related to device parameters.

You can write f0 SU0; (1)

fx SUx, (2)

where U0 and Ux are the voltages at the input of the PNCh T block;

fo and fx are the corresponding frequencies at the output of the FNP 1;

S is the slope of the FNP 1 conversion.

The number of pulses transmitted to the reversible counter 2 from the input of the direct count is equal to

N & f0 (t2-ti), (3)

from the entrance of the countdown account for the segment

Nx fx (t3-t2). (4)

Taking into account (1) and (2) and (3) and (4), it is possible to determine the number of pulses remaining in counter 2 by the time rz

N0-Nx S (U0-UxXt2-ti). (5)

The time () for filling the counter 3 is determined from

t4- ta

NQ-NX s (Uo-ux) (t2-ti)

su

(t2-tl).

(6)

And the number of Ng pulses, past the counter 2, is equal to

No

Uo - Ux 07

(t2-ti) frm.

(7)

five

0

0

five

0

five

0

five

0

where tgti is the frequency from the output of 3 clock generator 16, i.e.

Qk (t2 - ti) frm (8)

Obviously, the proportionality coefficient d is equal to the frequency ratio at the output 3 of the generator 16 clock pulses and at the input of the T-flip-flop 7. This frequency ratio can be chosen in such a way as to obtain the measurement result directly in the values of the measured conductivity.

The measurement range of the relative voltage is limited by the permissible time (tn - ta} filling the counter 3, which depends on the number of T-flip-flops connected in series. For an example implementation of a device

(t4-t3H2 (M-1) -1) (t2.-ti); . (9)

t4-t3

 7

In view of (9) of (6), we have

UQ UXMHH U - t3

2 (M-D. -I. (10)

UXMHHt2 tl

Where do we find the number of T-triggers, providing the required range of measurements

0 (m-1) Uo - Ux,, U0

Ux

M-1

+1

Uc

.

(eleven)

(12)

 Cumin

where Ux min is the minimum voltage value at the device input;

 - the whole part of the number X.

The proposed device makes it possible to measure the relative change of the decreasing voltages, is simpler than the known one, and provides a higher accuracy in measuring the dielectric losses in resonant dielectric-mass analyzers, for example, in Tangens-2M and W2-5 resonance dielectric meters. based on the direct replacement method. The principle of operation of dielectric meters is that the measuring circuit of the meter is alternately connected to the measuring circuit.

capacitive cell sensor or graduated capacitor. When a cell is connected, the LC circuit adjusts the resonance of a variable capacitor permanently connected to it, and when connected to the LC circuit instead of a graduated capacitor cell, the capacitor changes its capacitance. After tuning, the dielectric constant of the substance is determined on the scale of the graduated capacitor, and the conductivity dx, equivalent to the dielectric loss in the substance, is determined by the relative voltage variation on the LC circuit. Known

- L.

where Uo is the voltage on the circuit tuned to the resonance with the cell empty;

Ux is the voltage on the circuit tuned to the resonance after the test substance is introduced into the cell;

gk - constant - the intrinsic conductivity of the loaded circuit, is equivalent to the losses in its elements.

Due to the presence of active losses in the substance Ux Uo.

A layout of the proposed device was made and tested in a dielectric analyzer with positive results.

Claims (2)

An inventive formula 1. A device for measuring a relative voltage change, comprising a voltage-frequency converter, two keys, a reversible counter, a counter, a digital recording unit, a delay element, a control unit, the first output of which is connected to the control input of the first key, The forward counting input of the reversible counter is connected to the output of the first switch, the input of which is connected to the output of the voltage-frequency converter, so that, in order to extend the measurement range, additional and OR, Otrigser, the third key, the input of which is connected to the third output of the control unit, the output of the third key is connected to the counting input of the counter, the reset input of which is connected to the fourth output of the control unit, the reset input of the reversible counter and the first input of the second OR element, the voltage-frequency converter is the input of a device whose output is connected to the input of a second key, the output of which is connected to the counting input of a reversible counter, the output of the reverse transfer of which is connected en with the second input of the second element OR, the output of which connected to the reset input of the D-flip-flop, the recording input of which is connected to the second output of the control unit and the first input of the first OR element, the second input of which is connected to the output of the D-flip-flop, the control input of the third key and the input of the delay element whose output is connected to the second input digital registration unit, the first input of which is connected to the output of the counter, the output of the first element OR connected to the control input of the second key. 2. The device according to claim 1, characterized in that the control unit contains two M-input elements I, a reset pulse shaper, a pulse generator, the first input of which is connected to the input of the series-connected M T-triggers, and the first output of the block control is the output of the first element AND, the inputs of which are connected to the direct outputs of the first M-1 T-flip-flops and the inverse output of the last T-flip-flop. the direct output of which is connected to the return of the second element And, the remaining inputs of which are connected to the inverse outputs of the remaining T-flip-flops, the output of the second element And is the second output of the control unit, the third output of which is the second output of the clock pulse reset / Sa is connected to the output of the first element, And, and the number of M T-flip-flops is determined by the formula Uc , 4sM tt-. 3hmin where is the whole part of the number X; Uo is the value of the maximum voltage at the input of the device, relative to which the voltage change is measured; SO Ux min is the minimum voltage value at the device input. - -about- . G /. / S6 g -gch . (F G- / G j