SU839050A1 - Method and device for analogue-digital conversion - Google Patents

Description

The invention relates to digital electrical measuring equipment and may find application in the construction of integrating analog-to-digital converters. The known method of analog-digital conversion by push-pull integration, based on E41 integrating the input voltage during the first clock cycle, multiple to the network interference period, followed by integrating the reverse polarity reference voltage in the second clock cycle and quantizing the pulse of the reference frequency of the second clock interval LI. The disadvantage of this method is the effect on the accuracy of the distortion of the interference and its initial phase. The closest to the proposed method is the analog-to-digital conversion, which consists in integrating the input voltage during the first cycle in each conversion cycle, then integrating the reverse polarity reference voltage in the second cycle, and quantizing the sample voltage. Frequency interval time from the beginning of the second clock to the moment when the integrated voltage is equal to zero, after half the period of the mains voltage from the beginning of the first clock integrate the input voltage into ter A clock with a duration equal to the duration of the first clock, then integrate in the fourth clock the reference voltage of the reverse polarity to the input voltage, quantize the reference frequency with a pulse of the time interval from the beginning of the fourth clock to the instant that the integrated voltage is zero, the result of the conversion is defined as the half-sum of pulses received in the second and fourth cycles, and a device for carrying out the method, comprising a start-up unit and series-connected switching unit, The stator and the null organ whose output is connected to the input of the control unit, to the first input of the time interval generator and to the first input of the nepBdro key, the second input of the computer is connected to the first input of the time interval former, the second output of which is connected to the control input of the switching unit, two other input switching unit

connected to the input source gate and the source of the voltage source, the third input of the first switch is connected to the generator output of the reference frequency, and the output of the first switch is connected to the counting input of the first counter, whose information outputs1 through the first register-adder are connected to the inputs of the storage register The input of which is connected to the first output of the control unit, the second output of which is connected to the control input of the first register-adder 23.

The disadvantage of the present invention is the low accuracy of the analog-to-digital conversion under the action of an unbalanced voltage disturbance.

The purpose of the invention is more sophisticated.

The goal is achieved by the method of analog-to-digital conversion, which consists in integrating the input voltage during the first cycle in each conversion cycle, then integrating in the second cycle, the reverse voltage of the reverse polarity of the input voltage, and quantizing the sample frequency the time interval from the beginning of the second cycle to the moment when the integrated voltage is equal to zero, after half a period of the network voltage from the beginning of the first cycle, the input voltage is integrated into Then, in a fourth cycle, the reference voltage of reverse polarity is applied to the input voltage, quantized at an exemplary frequency pulses the time interval from the beginning of the fourth cycle to the instant that the integrated voltage is zero, the result of the conversion is defined as the half the number of pulses obtained in the second and fourth cycles, in each subsequent conversion cycle, the beginning of integration in the first and third cycles is shifted relative to the preceding q stem at a time interval proportional to the difference between the number of pulses received during vtorszh and fourth cycles.

Such a method can be implemented by a device containing a startup unit and a sequentially connected switching unit, an integrator and a null-organ whose output is connected to the input of the control unit, to the first input of the time interval generator and to the first input of the first key, the second input of which is connected to the first output The time interval generator, the second output of which is connected to the control input of the switching unit, the other two inputs of the switching unit are connected to the output of the input voltage source

the output of the reference voltage source, the third input of the first key is connected to the generator output of exemplary frequency, and the output of the first key is connected to the counting input of the first counter, whose information outputs are connected to the memory register through the first register-adder, the control input of which is connected to the first the output of the control unit, the second output of which is connected to the control input of the first register-adder, into which the second key, the second counter, the second and third registers-adders, and A code match block whose first information inputs are connected via the third and second adders to the information outcomes of the first counter, and the second information inputs to the information outputs of the second counter whose count input is connected to the output of the second key whose first input is connected to the output of the block start-up, the second input - with the output of the generator of exemplary frequency, and the third input -. with the output of the code match unit, the second input of the time interval generator and the reset inputs of the first and second counters, and the control inputs of the second and third adder registers are connected to the control inputs of the first registerjayMaTopa and memorizing register, respectively.

FIG. 1 is a timing diagram of the iterative process; in fig. 2 is a block diagram of a device implementing the method.

In nepBoiv | The conversion cycle at the moment when the mains voltage passes through the zero level (Fig. 1) begins the first cycle, in which the transformed voltage is integrated and, distorted by interference U,. The duration of the first cycle T is chosen in such a way that T, "T / 4, where T - period of interference. At the end of the first clock cycle, the second one begins, in which the reference voltage UQ is inverted to the input polarity. At the same time, a time interval T, n equal to the duration of the second clock, when the integrated voltage becomes zero to zero, is formed. This time interval is quantized by pulses of the exemplary frequency FQ and the number of pulses is determined proportional to the input voltage.

Claims (2)

At the next moment, the network voltage passes through the zero level, i.e. after half of the period of interference, the third cycle starts, in which the input voltage is integrated (the third time duration t. 1 is equal to the first time. At the end of the third cycle, the fourth time begins, in which the reference voltage UQ again integrates. As before the duration of the fourth and the same T and the number of pulses is proportional to the input voltage. The result of the N conversion is defined as NIX (,) / 2. This completes the first conversion cycle. The second conversion cycle differs from the first one in that The first and third cycles of conversion are shifted relative to the base in the first cycle by the value of LT, which is proportional to the difference. As in the first cycle, the time intervals T2Q and the number of pulses Nijj are determined, as well as the result of the conversion in the second cycle NQ, (Na.,) (2) In the t -th conversion cycle, at the start of the integration, in the first and third cycles, they are matched by an amount proportional to (T; -h, 2-T;., /, And the result of the conversion is determined (N / 2. The conversion process is carried out as long as () D is some valid value, determined by the allowable conversion error. The iterative process converges in the vicinity of the voltage transition of the noise through the zero level, regardless of its initial phase. In the worst case (in the absence of one half-wave interference), the conversion error brought to the input can be reduced by l, 6ot times where -T / 4T |. The smaller the interference distortion, the more the conversion errors will decrease. The convergence rate of the iterative process is 5-6 periods of interference and depends on the degree of distortion. The device (Fig. 2) contains the source 1 of the reference voltage, the switching unit 2, the integrator 3, the zero-body 4 / shaper 5 time intervals, the first key 6, the first counter 7, the generator 8 of exemplary frequency, the control unit 9, the first the recorder 10, the second register accumulator 11, the storage register 1, the third register-adder 13, the code matching block 14, the start block 15, the second key 16, the second counter 17. The inputs of the switch block 2 are given by measured voltage Ujj Ufl and output voltage of voltage source 1. The switching unit 2 is connected to the input of the integrator 3 in the first and third conversion steps, the input voltage Ux U, and in the second and fourth cycles, the voltage of the source 1 of the reference voltage. At the moment of reaching the output voltage of zero level, the zero-body 4 is triggered, the pulse pulse of which goes to the first input of the time generator 5 time intervals, to the First input of the first key 6 and to the input of the control unit 9. The second input of the key 6 is connected to one output of the Lormirovatel 5 time intervals, the other output of which is connected to the control input of the switching unit 2. The shaper 5 time intervals form the duration of the integration time intervals T. in the first and third cycles, as well as T and T in the second and fourth cycles. In this case, the second and fourth clock starts immediately after the first and third clock cycles, and their end is determined by the appearance of a pulse at the output of the null organ 4. During the durations of the second and fourth clock cycles, the counter 7 is filled with pulses of the reference frequency FO, which arrive in the counter 7 through the public key b from the output of the generator 8 exemplary frequency. The information clocks outputs of the first counter 7 are connected to the information inputs of the first and second registers-adders 10 and 11, respectively. Moreover, in the first register-adder 10, the results of the N conversion are summed up, in the second and fourth clock cycles | received in the counter 7, and in the second register-adder 11 - their subtraction HHie. After the fourth clock cycle, the results obtained in the first and second register-adders 10 and 11 are transferred to the storage register 12 and the third register-adder 13, respectively. The operation of the first, second, and third adder registers 10, 11, and 13, as well as the storage register 12, are controlled by the output signals of control unit 9. The information outputs of the third register-adder 13 are connected to the first inputs of a block 14G of matching codes, the second inputs of which are connected to the information outputs of the second counter 17, At the moment of equality of the codes of the second counter 17 and the third register-adder 13, an output appears at the output of block 4 of the codes which arrives at the second input of the imaging unit 5 time intervals, the reset inputs of both counters 7 and 17, and the third input of the second key 16. This pulse determines the beginning of the first and third integration cycles, as well as close The second key 16. The key 16 is opened by pulses from the input of the starting block 15, which are formed at the moments when the network voltage passes through the zero level. Pulses from the output of the generator 8 image of the juoBOSt frequency arrive at the counting input of the second counter 17 through the public key 16. During the public key 16, the counter 17 receives the number of pulses proportional to the code of a third of its register-adder 13, in which the differences of the second and fourth cycles are transformed . The integration time in the first and third cycles is selected on the basis that T m / 4, where T is the period of the interference voltage. The device works as follows. When the device is turned on, both counters 7 and 17. And registers 10-13 are set to zero. At the moment when the mains voltage goes over the zero level, it turns on the start 15 and opens its second key 16 with its output pulse. As a result, the pulses from the generator output 8 of the reference frequency begin to flow to the counter input of counter 17. When the state of counter 17 is equal to the register 13, block 14 is triggered by the fall of the codes, which, with its output pulse, closes the second key 16, resets both counters 7 and 17 to zero and turns on the driver 5 and the time intervals. The last for the time duration of the first cycle through the switch 2 connects to the input of the integrator 3 the input voltage and, and. At the end of the first clock cycle, the time interval imager 5 generates the next pulse, as a result of which the source 1 of the reference voltage is connected to the input of the integrator 3 via switch 2, the voltage of which is polarity opposite to the output voltage. At the same time, this pulse opens the first key 6, through which the counting pulses from the generator 8 output of the reference frequency begin to flow into the input of the first counter 7. When the integrator 3 reaches zero level, the zero-body 4 is triggered, the output pulse of which turns off the driver 5, time intervals , closes the key and turns on the control block 9. At the first output of the control 9, a pulse is generated which overwrites the state N of the counter 7 into registers 10 and 11. The next time the voltage goes over the network zero level again turned start unit 15 and the device operates as in the first two bars except that is performed every half-period interference in the counter 7 latched state, as in the third integration cycle, i.e. WITH OTHER HALF WAVE. In addition, the signal from the nepBdro output of the control block 9 in the register 10 fixes the number - () / 2, a the register 11 - d M - N (2- N, / ,, then the signal from the second output of the control block 9 registers 12 and 13, respectively, and registers 10 and 11 are zeroed in. This completes the first cycle of the device operation. In the second cycle, the device operates as in the first cycle, with the difference that the start of integration in the first and third cycles is shifted by D T is proportional to the number d N recorded in register 13. At the end of the second cycle in register 1 2 records the number NQX (N, j, -N2) 72, and in register 13 the number L N g d N, f U N5, where & Nj g N25 is Nj, and FOR the conversion results in the second and fourth cycles of the second cycle conversion. In the “- that conversion cycle, the offset of the start of integration in the first and third cycles relative to the first cycle is determined by the value proportional to 2. The result of the conversion is defined as N. ,, 4N;,.,) / 2. As a result of this iterative process, the start points of the integration in the first and third cycles are automatically chosen such that the input signal is integrated in the vicinity of the zero-level noise transition, regardless of the initial phase of the interference. Claim 1. Analog-to-digital conversion method, which consists in integrating the input voltage during each conversion cycle during the first cycle, then integrating the reverse voltage of the input voltage in the second cycle, quantizing the reference frequency with time interval from the beginning of the second cycle to the moment when the integrated voltage is zero, after half a period of the network voltage from the beginning of the first cycle, the input voltage is integrated in the third cycle, the duration u, equal to the duration of the first cycle, then integrate in the fourth cycle the reference nagging of the inverse polarity to the input voltage, quantize the interval, the time from the beginning of the fourth cycle to the zero point of the integrated voltage, by quantizing the reference frequency pulses, the result of the conversion is the half-sum of the number of pulses, obtained in the second and fourth cycles, characterized in that, in order to increase accuracy, in each subsequent transformation, the beginning of the integration in the first and third cycles shift relate the previous cycle for the time interval proportional to the difference in the number of pulses received in the second and fourth cycles. 2. The device according to claim 1, comprising a startup unit and a sequentially connected switching unit, an integrator and a null-orgai, the output of which is connected to the input of the control unit, to the first input of the time slot and to the first input of the first key, the second input of which is connected to the first output of the time interval generator, the second output of which is connected to the control input of the switching unit, two other inputs of the switching unit are connected to the output of the input voltage source and the output of the reference voltage source, third The input of the first key is connected to the generator output of an exemplary frequency, and the output of the first key is connected to the counting input of the first, whose information outputs are connected through the first register-adder to the inputs of the memory register, the control input of which is connected to the first output of the control unit, the second output of which is connected to the control input of the first register-adder, characterized in that. that the additional key, the second counter, the second and third registers-adders, and the block of coincidence codes, the first information inputs of which are connected through the third and second registers-adders to the information outputs of the first counter, and the second information inputs - to the information outputs of the second a counter whose counting input is connected to the output of the second key, the first input of which is connected to the output of the startup unit, the second input to the generator output of the reference frequency, and the third input to the output of the code matching unit, the second input of the time interval generator and the reset inputs of the first and second counters, and the control inputs of the second and third registers of the summers are connected to the control inputs of the first register-adder and 0 storage register, respectively. Sources of information taken into account in the examination 1, Shl ndin V.M. Digital measurements of transducers and devices. M., Higher School, 1973, p. 185-187. 2. Prinishnikov V.A. Integrating digital DC voltmeters. 1976, p. 88-81, fig. 2-12 0 (prototype). ig.2 "I