SU1751685A1 - Device for measuring power - Google Patents

Abstract

Usage: power sensor in control systems of large power generators. The essence of the invention: the device contains a current-voltage converter, two analog-digital converters 3 and 4, two operational storage units 5 and 6, a control unit 2, a microprocessor calculator 7, an indicator 8. 1-3-5-7-8, 4 -6-7, 2-4-6, 2-3-5, 2-6, 2-5, 2-7, 7-2. 1 hp f-ly, 4 ill.

Description

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The invention relates to a digital measuring technique and an electric drive and can be used as a measuring device and a power sensor in the control systems of large generators.

A digital power meter is known, which contains two input devices, two analog-digital converters (or analog-code converters), a control unit, a frequency multiplier, a digital distributor of sampling points, a multiplying device, two electronic switches (or a pulse-potential valve), a trigger and two reverse counters. The disadvantages of this wattmeter are a large measurement time in the low frequency range, limited functionality, the complexity of the measurement process and low reliability. The closest to the present invention is the AC and DC power meter D5135, which contains two analog-digital converters, two comparators, a current-voltage converter, a control unit, a display unit, a microprocessor computer, and a random access memory.

The disadvantages of the known meter are the large measurement time in the low-frequency range and the narrow class of the Solved Problems, since it does not allow to measure the total power, the power factor (cozy power) and the sin p value.

The purpose of the invention is to increase the measurement speed in the low frequency range and enhance the functionality by measuring the total power, the power factor cos p and the value of sin p.

The goal is achieved by the fact that the device for measuring power, containing the first and second analog-digital converters, current-voltage converter, control unit, display unit, microprocessor calculator, random access memory, and the signal input of the first signal terminal. the converter is connected via a current-to-voltage converter With the first input of the device, a second operational storage unit is additionally introduced, with the information outputs of the first and second analog-digital signals drivers are connected respectively to the information inputs of the first and second operational storage blocks, and the outputs. The end of the conversion of analog-digital converters are connected to

the gating inputs of the recording of the corresponding operational storage blocks, the address inputs of which are combined into a common bus connected to the second output

5 of the control unit, and the outputs of the first and second random access memory blocks are connected to the first and second information inputs of the microprocessor computer, which by its control

0 is connected to the third output of the control unit, the control output is connected to the second input of the control unit, and the information output is connected to the input of the display unit, and the signal

5 the input of the second analog-to-digital converter is combined with the first input of the control unit and connected to the second input of the device, and the start inputs of the analog-digital converters are connected to the first

0 by the output of the control unit.

The goal is achieved by the fact that the control unit contains a null-organ, an exemplary frequency generator, the first and second frequency dividers, the first and second

5 subtractive counters, register, pulse counter, first, second, third, fourth and fifth triggers, first, second, third, and fourth elements AND, first, second, third, and fourth elements OR, first.

0 the second and third delay elements, the pulse shaper, the Start button and the switch having three switching contacts, the first input of the control unit is connected to the input of the null organ,

5 whose output is connected to the first inputs of the first and second elements I, connected by their second inputs to the direct outputs of the first and second triggers respectively, the installation input of the first trigger

0 is connected via the first delay element and pulse generator with the Start button, and the reset input is combined with the input of the second delay element and the first input of the fourth OR element and connected to the cinema output of the third trigger, the counting input of which is connected to the output of the first And element, and the forward output - with the first input of the third element And, the second input of which is connected to the output of the generator

0 of the reference frequency and the first input of the fourth element I, connected by its second input to the direct output of the fourth trigger, the output of the third element I is connected through the first frequency divider with

5 by the counting input of the pulse counter, and the output of the second element I, with the combined counting input of the second frequency divider and the first fixed contact of the switch, the second fixed contact of which is connected to the output of the second divider

frequency, and the first movable contact is connected to the installation input of the fourth trigger connected by its reset input to the output of the first OR element, the first input of which is connected to the third fixed contact of the switch and the first input of the fourth OR element, the output of which is connected to the register entry input and the third element input delay connected by its output to the first input of the third OR element, the second input of which is connected to the fifth fixed contact of the switch, the information input of the register is connected to one output of the pulse counter, and the output of the register bit is connected to the code input of the first subtractive counter connected by its counting input to the output of the fourth AND element, the write input to the output of the third OR element and the loan output to the combined first input of the control unit and the third moving contacts of the switch and the first input of the second element OR, connected by its second input to the second input of the control unit, and its output to the counting input of the second subtractive counter, information the output of which is connected to the second output of the control unit, and its counting input is connected to the reset input of the second trigger connected by its installation input to the output of the second delay element, and the installation input of the fifth trigger, whose direct output is connected to the second input of the first OR element and the third output of the control unit, the direct output of the second trigger is connected to the second input of the second element I.

The proposed device for power measurement is characterized by the introduction of a second operative storage unit and functional connections between the input and known units of the device.

The essence of the invention is that it is based on the correlation processing of samples of instantaneous values of voltage and current, which is carried out in two stages: first, the accumulation of samples, and then their processing in a universal microprocessor calculator to determine the measured values.

The presence of an inserted unit with functional connections between known prototype nodes reduces the measurement time in the low-frequency range and extends the functionality by measuring the total power, the power factor cozy and sin p, as well as the voltage and current characteristics. Control units are also widely used in digital measuring devices and devices, however, the construction of a control unit in the proposed device is determined by the algorithms for obtaining current and voltage readings and their processing, as well as the principle of building devices, i.e. It is specific to this device.

Fig. 1 shows the structural electrical circuit of the proposed device for power measurement; in fig. 2 is a structural electrical circuit of the control unit; Fig. 3 is a structural electrical circuit of a microprocessor computer; in fig. 4 - timing charts of the control unit.

A device for measuring power contains a current-voltage converter 1, a control unit 2, first and second analog-digital converters (ADC) 3 and 4, first and second operational storage units (03B) 5 and 6, a microprocessor calculator 7 and display unit 8 (figure 1) ./

The first, current, input of the device for measuring the power through the converter T is the current-voltage connected to the signal input of the A / D converter 3, and the second to one, the voltage input is connected to a point combining the signal input of the A / D converter 4 and the first input of the control unit 2. The start inputs of the ADC 3 and L are interconnected and connected to the first output of the control unit 2. Information outputs of the ADC 3 and 4 are connected to the information inputs (data inputs) of the OZB 5 and 6, respectively. Output The conversion end of the A / D converter 3 is connected to the input gate of the recording of AZB 5, and the output of the conversion of the A / D converter 4 is connected to the input gate of the recording of AOZ 6. The address inputs of OZB 5 and b are combined into a common bus connected to the second address output of control unit 2 and their outputs connected respectively to the first and second information inputs (data inputs) of the microprocessor computer 7, the control input of which is connected to the third output of the control unit 2. The control output of the microprocessor computer 7 is connected to the second input of the control unit 2, and its information output is connected to the input of the display unit 8.

The control unit 2 contains a zero-authority 9, an exemplary frequency generator 10, elements 11-11, triggers 15-19, frequency dividers 20 and 21, subtracting counters 22 and 23, a register 24, a counter 25 pulses, delay elements 26-28; , elements OR 29 - 32, pulse shaper33, button 34

Start, switch 35 Frequency range, having three switching contacts 35-1, 35-2 and 35-3 (figure 2).

The first signal input of control unit 2 is connected to the input of the null organ 9, the output of which is connected to a point connecting the first inputs of elements 11 and 12. The second input of element 11 is connected to the forward output of the trigger 15, the input of which is connected through element 26 delay and pulse shaper 33 with a button 34 Start. The pulse shaper 33 serves to eliminate the effect of the rattling of the Start button 34, which eliminates failures at the start of the device. The reset input of trigger 15 is combined with the input of delay element 27 and with the first input of element OR 32 at a point connected to the inverse output of trigger 17, the direct output of which is connected to the first input of element 13. The output of delay element 27 is connected to the installation input of trigger 16, the direct output of which is connected to the second input of the And 12 element. The output of the And 12 element is connected to the point connecting the input of the frequency divider 21 and the fixed contact 3 of the switch 35. The output of the frequency divider 21 is connected to the fixed contact 2 of the switch 35, the movable contact kt 1 of which is connected to the input of the installation of the trigger 18, connected by its direct output to the first input of the And 14 element. The second inputs of the And 13 and 14 elements are interconnected and connected to the output of the generator 10 of exemplary frequency. The output of the And 14 element is connected to the counting input of the detracting counter 23, and the output of the And 13 element is connected via a frequency divider 20 to the counting input of the pulse counter 25, the code output of which is connected bitwise to the information (code) input of the register 24 connected by its code output with the information (code) input of the subtracting counter 23. The loan output of the subtractive counter 23 is connected to the point combining the first output of the control unit 2, the first input of the element OR 30 and the moving contacts 4 and 7 of the switch 35. Fixed to Ontact 8 of switch 35 is connected to the first input of the OR element 29, the output of which is connected to the reset input of the trigger 18, and to the second input of the OR element 32, the output of which is connected to the point uniting the input of the register entry 24 and the output of the delay element 28 connected by its output with the first input of the element OR 31, the second input of which is connected to the fixed contact 5 of the switch 35. The output of the element OR 31 is connected to the recording input of the subtractive

counter 23. The second input of the element OR 30 is connected to the second control input of the control unit 2, and the counting input of the down counter 22 is connected to its output,

the information (code) output of which is connected to the second, address, output of control unit 2. The output of the loan counter 22 is connected to a point combining the reset input of the trigger 16 and the installation input of the trigger 19, the direct output of which is connected to the second input of the OR element 29 and the third output of the control unit 2. The fixed contacts 6 and 9 of switch 35 do not have electrical connections, and in position II

5, the switch 35 of their circuit is broken.

The relief circuits of the elements and components of the control unit 2 for simplifying the circuit are not shown.

0 The microprocessor computer 7 is assembled on a single-chip microcomputer KR1816BE51 and contains a single-chip micro-computer (OMELM), a decoder 36, register 37, counting trigger 38, operational

5 a storage unit (OZB) 39 and a permanent storage unit (PZB) 40 (FIG. 3).

The control input of the microprocessor computer 7 is connected to the input of the VPD / RST OMABM and is intended to enable it

0 work. The two information inputs of the microprocessor computer 7 are connected directly to the ports P1 and RZ OMABM, the other two ports (PO and P2) are distributed as follows. Port RO,

5, which is used in the bidirectional mode of operation, is connected to the internal backbone of the microprocessor computer and serves for transmitting the address and data exchange between the OMELV and the PSA 39, the OTDR 40.

0 The internal bus of the computer is formed when the data inputs of the register 37 and the OZB 39 are merged in one way, and the OZB 39 and the OZB 40 are output. In addition, the internal highway together with the port

The 5 P2 PDSs are the information output of the microprocessor calculator 7. At the same time, information is transmitted along the internal line to the display unit 8, which is controlled by the P2 port.

To ensure the synchronous operation of the register 37 of the OZB 39, the PZB 40 and OMATM are the PSEN and ALE / PROG OMABM outputs, which are connected to the inputs of the decoder

5 36. On the first output of the decoder 36 (ALE) connected to the clock input of the register 37, the recording of the address of the polled cell of one of the storage devices is gated. 03B 39 is controlled by a signal from the second (WR) and third (RD) outputs of the decoder 36 connected to the enable inputs of the write and read information, respectively. The fourth (PME) output of the decoder 36, which is connected to to the control input of the ZGP 40. In addition, the ALE output of the decoder 36 is connected to the input of the counting trigger 38, the direct output of which is the control output of the microprocessor computer 7. The address inputs of the ZVB 39 and the ZZB 40 are combined and connected to the output of the register 37.

Consider the principle of operation of the proposed device for measuring power.

The current l (t) (fig. 4, a) of the circuit under study is fed to the converter 1 by the first input of the device - a voltage (fig. 1), by which it is converted into a proportional voltage drop.

Ui (t) Ki i (t).

where KI is the current transfer coefficient of the converter 1 - voltage.

The voltage Ui (t) from the output of the converter 1 is the current - the voltage goes to the signal input of the ADC 3. The voltage U (t) (FIG. 4, a) of the circuit under study is fed to the signal input of the ADC 4 and to the first signal control unit 2 input. In the initial state, the A / D converters 3 and 4 are in the standby mode and are switched to the conversion mode by start pulses arriving at their start inputs combined with each other from the first output of the control unit 2.

The operation of the device proceeds in two stages: at the first stage, using ADCs 3 and 4, they receive codes of instantaneous values of current and voltage U (t) and write them to OZB 5 and 6; at the second stage, all measured values are determined by these codes using a microprocessor calculator 7.

The first measurement stage starts with the Start signal generated in the control unit 2 by pressing the Start button 34 (Fig. 2). In this case, a pulse is generated at the output of the pulse driver 33, which is fed to the reset bus to set the device to its initial state and to the delay element 26. A reset pulse, subtractive counter 23, register 24 and counter 25 pulses are zeroed in, and subtract counter 22 records the number n equal to the number of sampling points per period T of the input signals. The division factor L of the frequency divider 21 is equal to the number of periods through which each successive

the time of discretization η, starting from the first:

 At + (q-1) LT ,, n, where.

5Pri, i.e. when sampling signals over a period T, the value of At represents the interval or discretization step. However, in the initial state, a number (2-1) is written to the frequency divider 21, where I is its width, i.e., the maximum number is written into it (or all of its triggers are set to one).

The division factor of the frequency divider 20 is set to n.

5 The coefficients n, L can be as constant (then they are sewn up rigidly or schematically). and variable (set by switches from the front panel of the device).

0 The triggers 15-19 of the reset pulse control unit 2 are set to zero and the low level signals from the direct outputs of the triggers 15-18 are closed, respectively, AND 11-14 elements.

5 The voltage U (t) at the first signal input of the control unit 2 is fed to the input of the zero-organ 9, at the output of which at the moments of transition of this voltage through zero values from short to positive pulses short pulses are formed (Fig. 4,6) but they do not pass through elements 11 and 12.

Through the delay time specified by the delay element 26 and selected from the condition of termination of transients when the circuit is reset, the Start pulse (Fig. 4, c) enters the input of the trigger 15 and switches it to one, opening the element AND

0 11 to pass pulses from a null organ 9. The first pulse V1 (Fig. 4.6), coming from the output of the null organ 9 through the element 11 to the counting input of the trigger 17, sets it to one state.

5 A high level signal from the direct output of the trigger 17 separates the element I 13, and the pulses of the exemplary frequency f0 from the output of the generator 10 are fed to a frequency divider 20, the output pulses of which are accumulated by the pulse counter 25 pulses. The second output pulse V2 (Fig. 4,6) of the null organ 9, which enters through the open element AND 11 to the counting input of the trigger 17, returns this trigger to the initial zero state,

5 A low level signal from the direct output of the trigger 17 and the element 13 is closed. During the open state of the element And 13, equal to the period T of the input signals of the device, the number divider NT (figure 4, d) equal to: Mt-T fo, is supplied to the frequency divider 20,

and the number of pulses N is recorded in the pulse counter 25 (Fig. 4 d). equal to:

 ,

The high level signal from the inverted output of the trigger 17 is fed to the reset input of the trigger 15, to the input of the delay element 27 and to the first input of the OR 32 element. The trigger 15 returns to its original zero state, closing the AND 11 element to pass the output zero-body pulses 9. From the output of the OR element 32, the signal is fed to the input of the record of register 24, and also through the element 28 of the delay and the element OR of 31 to the recording input of the subtractive counter 23. With this signal, the N code is first transferred from the counter of 25 pulses to the register 24, and then with some delay defined th recording time number in register 24, the code N from the register 24 is written in the down counter 23, Thereafter, the signal from delay element 27 is supplied to the flip-flop 16 set input, setting it in a single state. The high level signal from the direct output of the trigger 16 opens element 12 for passing pulses from the output of the null organ 9 through it.

Further operation of control unit 2 depends on the frequency range of the input signals and has two modes: LF (low frequencies) and HF (high frequencies). These modes are set by switch 35. Consider each of these modes.

In the RF mode, the switch 35 is in position I. In this case, the input of the installation of the trigger 18 by the switching contact 35-1 is connected to the output of the frequency divider 21, the second input of the element OR 31 by the switching contact 35-2 and the point connecting the second input of the element OR 32 and the first input element OR 29, the switching contact 35-3 is connected to the output of the loan of the subtraction counter 23. The first impulse V3 from the output of the zero-organ 9, arriving at the time instant tot (Fig. 4.6) through the open element And 12 zeroed the divider 21 frequencies and at its output a pulse is generated, which In the divider itself, the division factor LM at the installation input switches trigger 18 to one state. The high level signal from the direct output of trigger 18 opens element 14 and the pulses with frequency f0 from generator 10 of exemplary frequency are fed to subtractive counter 23 until it is zeroing at the time ti. To this point in time 0

The counting counter 23 receives the number of pulses N of the frequency f0 and a start pulse V3i is formed at the output of the loan (FIG. 4, e), which is fed through the first output of control unit 2 to the combined start inputs of the ADC 3 and 4. The start pulse V31 will be located relative to the start Countdown toi through time interval

N / f0.

P To P

At the inputs of the ADC G and 4, the codes are formed: NH-CACCP Ui (ti) KAun Ki l (ti); NUI-KACP U (ti) KAUn U (n), where KACP is the transfer coefficient (or conversion) of the ADC;

i (ti), U (ti) are the instantaneous values of current and voltage at time ti.

The MI and NUI codes from the information outputs of the A / D converters 3 and 4 are recorded, respectively.

in 03B 5 and 6 by signals End of conversion from the outputs of the A / D converters 3 and 4 to the gates of the recording of DZB 5 and 6. The addresses of AZB 5 and 6 are given by the code from the information output of the down counter

22 supplied by the second output of the control unit 2 to the address inputs of the AOZ 5 and 6. The same starting pulses from the output of the deducting counter 23 are sent to the counting input of the detracting counter 22 via the element

OR 30. In addition, the output pulse of the subtractive counter 23 through the switching contact 35-3 enters, firstly, through the element OR 29 to the reset input of the trigger 18, and, secondly, through the element OR 32

- to the input of the record of register 24 and through the delay element 28 and the element OR of 31 to the input of the record of the subtractive counter 23. The trigger 18 is set to the initial zero state, closing the element And 14, into the register

24 is transferred the code of the number N from the counter 25 pulses and its readings become 2N; Then the code of the number 2N is written into the subtractive counter 23. The circuit is in this state until the next pulse from the output of the frequency divider 21 to the trigger setup input 18. This pulse is formed after the L output pulse 9 of the output organ 9 arrives at the frequency divider 21 input through open item and 12.

For compactness of the time diagram (Fig. 4, e), we accept what is meant by setting each sampling time tq through the period of input signals, i.e. in each period, only one sample of the instantaneous signals l (t) and U (t) is obtained. In this case, with the arrival of the next pulse V4 at the time moment to2 (Fig. 4.6), from the null organ 9 to the input of the frequency divider 21, a pulse is formed at the output of the latter, which sets the trigger 18 on its installation input to the unit state, opening the element And 14. The pulses of frequency f0 from the generator 10 are fed through the open element AND 14 to the counting input of the subtractive counter 23 before zeroing it, at which a second trigger pulse V32 is formed at its loan output (Fig. 4, e). It will be located relative to the reference time to2 through the time interval

2N / f0 - 2-2At.

PTOP

The V32 trigger pulse performs the same operations as the V31 trigger pulse. In this case, in the register 24, and then in the subtractive counter 23, the code of the number 3N will be recorded and the next launch pulse V33 at its output will be generated relative to the reference time, wz, via the time interval

3N / f0 2 3At.

PTO

Subsequently, the operation of the control unit 2 repeats as before and the start-up pulses will be generated at times tq, which are at a distance of qAt from the beginning of each successive period, which corresponds to the sampling interval At, while the sampling points are distributed through one period of input signals.

With another number L, the operation of the control unit 2 is preserved, the difference is that the pulses at the output of the frequency divider 21 are formed through the L output pulses of the zero-organ 9 and thus the reference times toa are shifted by L periods. toaton.

This continues until all the n sampling points tq or trigger pulses are set at the output of the subtracting counter 23, after which the subtractive counter 22 is zeroed. At its loan exit, a pulse is generated, which is fed to the reset input of trigger 16 and to the trigger setup input 19. Trigger 16 returns to the initial zero state, closing element 12. Trigger 10 switches to one and a high level signal My output, which is the third output of control unit 2, is supplied to microprocessor calculator 7 via its control input. Element 14 closes with a low level signal from the direct output of the trigger 18 set to the zero state. In this operation, control unit 2 stops and the first measurement stage ends. In 03 B 5 and 6 will be

Codes Niq and Nuq,, n, instantaneous values of current l (t) and voltage U (t) are recorded.

In the bass mode, the switch 35 is set to position II. In this mode, sampling moments tq are set for one period of the input signals (FIG. 4, g). Until time ti (the formation of the first start pulse V3i), the device and its control unit 2 work in a similar way, the difference

0 is only that the input of the installation of the trigger 18 impulse zero-body V3 enters the output element And 12 through the switching contact 35-1. The main difference in the operation of the device is due to the formation of the remaining V32 trigger pulses.

U3zV3n at the output of the deducting counter

23, which follow with the discretization step At. To provide this time interval, the number of pulses N recorded in it is saved in register 24, since the circuit for writing code to register 24 from counter 25 is impulses V32, V33, ..., V3n from the output of the subtracting counter 23 through switching contact 35- 3 torn. And this number

5 pulses N with the same pulses V32, U3zV3n from the output of the loan of the subtractive counter 23 through the closed switching contact 35-2 and the element OR 31 are recorded in the subtractive counter 23. H8 is countable

0 the input of the subtracting counter 23 pulses of the exemplary frequency f0 from the output of the generator 10 are fed through the open element I14 continuously throughout the period T of the input signals limited by pulses

5 V3 and V4 from the output of the null organ 9 (Fig. 4, g). Element I 14 is open in this interval by a high level signal from the direct output of flip-flop 18, since this flip-flop remains in one state until the formation of a Uzp pulse at the output of the deducting counter 23. All others

V31, V32V3 (n-i) pulses on trigger 18 not

affect, as in the previous mode, as the switching contact 35-3

5 their supply chain through the element IL AND 29 is broken at the reset input of this trigger. At the time tn of the formation of the last pulse V3n (FIG. 4, g), the output counter 22 has zeroed at the output of the loan of the subtractive counter 23, and, as in the previous mode, the trigger 16 is reset to its initial state by closing the element is And 12, and the trigger 19 is switched to one state. With

5 this high level signal from its direct output, coming through the element OR 19 to the reset input of the trigger 18, the latter is set to the initial state, closing the element AND 14. The same signal on the third output of the control unit is fed to the control input of the microprocessor computer 7 .

As in the first mode, this completes the first stage of the second mode and begins the second stage of operation of the device, in which the microprocessor computer 7 determines the required measured characteristics,

The signal from the direct output of the trigger 19, which enters the microprocessor computer 7, brings it to the operating mode. At the same time, with the arrival of a clock pulse, the output of the PME of the decoder 36, which actually converts the control code combinations at the output of the OM computer, sequentially, step by step, the instruction codes defining the operation algorithm of the OM computer 40 are read out. intermediate results are carried out in the RRB 39, and the information is recorded at the output WR of the decoder 36, and the reading at the output RD. The address of the memory cell (03B39 or FBB 40) is generated in the OM computer and, at the command of the ALE output of the decoder 36, is written into the register 37, in which it is stored. All control signals (ALE, WR, RD, and PME) are mutually exclusive, therefore the organization of data exchange between the internal nodes of the microprocessor calculator 7 is performed by software when operating the OM computer. Such an operation of the microprocessor computer 7 is standard and does not require additional explanations.

When the microprocessor computer 7 is in operation, the Niq and Nuq,, n codes from OZB 5 and 6 are initially read, and then processed. The reading of codes and Nuq by the microprocessor computer 7 is carried out on its first and second information inputs. In this case, the addresses of cells OZB 39, in which the next pair of codes Niq and Mcdall of some value q in the range, n, are written, are formed by an OM computer. The setting of these addresses in register 37 is accompanied by a clock pulse from the ALE output of the decoder 36. When each pair of addresses changes, which corresponds to rewriting codes from the two inputs of the microprocessor computer 7, a pulse is generated at the output of the counting trigger 38, which on the control output of the microprocessor computer 7 is fed to the second input of control unit 2 through the OR element 29 to the counting input of the detracting counter 22. With the arrival of each pulse, the addresses of all n numbers written in OZB 5 are sequentially generated with this counter 6.

At the end of the rewriting cycle, the first and second information inputs of the microprocessor computer 7 are programmatically disabled and it proceeds to the sequential calculation of the following energy characteristics: active power

Mr

4 t

 K | ц i t i (tq) UCtq) Kp-P;

q 1 reactive power

 | iN, qNu (q + n)

 Kytsp Dyuch) Ufo +}) Kp-Q,

where Nuq codes are programmed from HZB 6 with a shift by n / 4 addresses relative to Niq codes from HZB 5, which is equivalent to a phase shift by 1: 2 voltage and current needed to determine the reactive power:

full power

Ns VNЈ + Nk KPVp2 + Q2 KP-S;

power factor Np P

Ncosp u jr cos r;

slnp value

In addition, rms (effective) values of voltage and current, average values of voltage and current, average modulo (average direct) values of voltage and current, phase shift can be determined by known formulas.

Thus, the use of the proposed device in the construction of digital universal power meters allows reducing their measurement time and expanding functionality, which provides improved performance and reliability of measurements, simplifying the measurement process and obtaining an economic effect.

Claims (2)

1. Power metering device containing first and second analog-to-digital converters, current-voltage converter, control unit, display unit, microprocessor calculator, on-line storage unit, while the signal input of the first analog-digital converter is connected via a current-voltage converter. with the first input of the device, characterized by the fact that, in order to increase the speed in the low-frequency range and to expand the functionality by changing the total power, cos p p power factor and sin p values, the second random access memory block is inserted into it, the information outputs of the first and second analog-digital converters are connected respectively to the information inputs of the first and second operational memory blocks, and the outputs of the conversion of analog-digital converters are connected to the inputs write gates of the corresponding operational storage blocks, the address inputs of which are combined into a common bus connected to the second output of the control unit, and the outputs The first and second operational storage units are connected to the first and second information inputs of the microprocessor computer, which by its control input is connected to the third output of the control unit, the control output is connected to the second input of the control unit, and the information output is connected to the input of the display unit, with the signal input the second analog-digital converter is combined with the first input of the control unit and connected to the second input of the device, and the start inputs of the analog-digital converter connected to the first output of the control unit. 2. The device according to claim 1, characterized by the fact. the control unit contains a zero-body generator of an exemplary frequency., the first and second frequency dividers, the first and second subtractive counters, register, pulse counter, the first, second, third, fourth and fifth triggers, the first, second, third and fourth elements AND , first, second, third and fourth elements OR. first, second and third delay elements, pulse shaper, start button and a switch that has three switching contacts, the first input of the control unit connected to the input of the zero-body, the output of which is connected to the first inputs of the first and second elements And connected to their second inputs to the direct outputs of the first and second triggers, respectively, the installation input of the first trigger is connected via the first delay element and the pulse shaper to the Start button, and the reset input is combined with the input of the second the delay element and the first input of the fourth element IL AND, and is connected to the inverse output of the third trigger, the counting input of which is connected to the output of the first 5 element I. And the direct output is connected to the first input of the third element And, the second input of which is connected to the output of the generator of the reference frequency and the first input of the fourth element And, connected by its 0 by the second input with the direct output of the fourth trigger, the output of the third element I is connected through the first frequency divider with the counting input of the pulse counter, and the output of the second element I - with the combined 5 by the counting input of the second frequency divider and the first fixed contact of the switch, the second fixed contact of which is connected to the output of the second frequency divider, and the first moving contact is connected to the installation input of the fourth trigger connected by its reset input to the output of the first element OR, the first input of which is connected to the third fixed contact switch at the first input 5 of the fourth OR element, the output of which is connected to the input of the register record and the input of the third delay element connected by its output to the first input of the third OR element, the second input of which is connected to the second fixed contact of the switch, the information input of the register is connected to the code output of the pulse counter , and the output of the pore register register is connected to the coaxial input of the first subtractive counter, connected by its counting input to the output of the fourth AND element, the recording input - with the output of the third OR element, and loan exit - with the united first exit of the block 0 control, the second and third movable contacts of the switch and the first input of the second OR element connected by its second input to the second input of the control unit, and its output to the counting 5 to the input of the second subtractive counter, the information output of which is connected to the second output of the control unit, and its counting input is connected to the reset input of the second trigger connected by its input 0 setting with the output of the second delay element, and the installation input of the fifth trigger, the direct output of which is connected to the second input of the first OR element and the third output of the control unit, direct output 5 of the second trigger is connected to the second input of the second element I. AND I FIG 2 i c ± a I I Ui TT