SU1725231A1 - Device for monitoring states of complex dynamic systems - Google Patents

Abstract

The invention relates to automation and can be used in control systems of objects with a discrete nature of the technological cycle. The aim of the invention is to expand the functionality of the device due to the possibility of fixing parametric faults of elements of a complex system. The device contains the first and second registers, the first and second memory blocks, a counter, a block of elements ADDITIONAL BY MODULE TWO, a pulse shaper, an OR element, a block of AND elements, an OR-NOT element, a clock generator, an I. element, 1 Il.

Description

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The invention relates to automation and can be used in control systems of objects with a discrete nature of the technological cycle.

A device for controlling complex systems is known in which the output signals of a control object are connected in series with a switch to a comparison unit, where they are compared with the corresponding constant settings stored in a memory unit.

The disadvantage of the device is the inability to control the dynamics of the operation of complex systems.

It is also known to control the sequence of operation of logic circuits, containing a series of blocks for comparing logical signals, a counter. The device allows to optimize the system operation in each folding situation 1.

The drawback of the device is the lack of means to compensate for the undesirable effects of transients that occur when the state of the controlled system changes.

The closest to the present invention is a device for controlling the dynamics of complex systems, which contains two registers, a memory block, a block of elements. CONSTITUTION ON A MODULE TWO, a block of AND elements, an OR element, and a clock generator.

PI The disadvantage of this device is the impossibility of fixing parametric failures of a complex system, i.e. States arising from the introduction of the system in a static mode of operation. When parametric failures occur

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the system does not change its state, as a result of which the monitoring device will be in a state of waiting for the next state. Consequently, the device in question does not allow fixing disturbances in the dynamics of the functioning of a complex system caused by parametric failures.

The aim of the invention is to expand the functionality of the device due to the possibility of fixing parametric failures of elements of a complex system.

To achieve this goal, a device for controlling complex dynamic systems containing the first and second registers, the group of elements is COMPLEX BY MODULE TWO, the first block of standards memory, the group of elements AND, the clock generator, the element OR, and the information inputs of the first register are The inputs of the device for connecting the outputs of the monitored system, and the outputs are connected to the information inputs of the second register and the first inputs of the elements. COMPOSITION BY MODULE TWO groups, the second inputs of which are connected to the output The second register and the group of address inputs of the first memory block of the standards, and the outputs are connected to the inputs of the OR element and the first inputs of the corresponding AND elements of the group, the second inputs of which are connected to the output group of the first memory block of the standards of standards, a counter, a pulse shaper, an AND element and an OR-NOT element, the first input of which is connected to the counter overflow output, and the remaining inputs to the outputs of AND elements of the group, the output of the OR element is connected to the input of the importer The output of which is connected to the control input of the parallel loading of the counter, the setup inputs of which are connected to the outputs of the second memory module of the standards, the address inputs of which are connected to the outputs of the first register, the output of the OR-NOT element, which is the output of the device, is connected to the first input element I, the second input of which is connected to the output of the clock pulse generator, and the output is connected to the clock inputs of the first and second registers and the counting input of the counter.

The second block of standards memory stores codes, each of which corresponds to the maximum time the controlled system is in one of the possible states. The counter monitors the time intervals corresponding to the codes received from the second memory of the standards.

The pulse shaper is generated by a signal coming from the OR element (system state change signal), which generates a pulse to load the code corresponding to the new system state to the counter. The element OR- does not fix the transition of the system to one of the unacceptable technical conditions or the occurrence of a parametric failure, i.e. expiration of the time allotted for this state. In both cases, a logical O signal appears at the output of the element, informing about abnormal system operation and blocking the passage of clock pulses through element I.

The drawing shows a diagram of a device for controlling complex systems.

The device contains the first 1 and second 2 registers, the first 3 and second 4 memory blocks of the standards, counter 5, group 6 elements COMPLEX ON MODULE TWO 7, driver 8 pulses, element OR 9, group 10 elements AND 11, element OR NOT 12 clock generator 13 and element 14. The outputs of register 1 are connected to the inputs of memory block 4, the group of inputs 15 of register 2 and the first inputs of elements 7 of group 6, the outputs of which are connected to the inputs of element 9 and the first inputs of elements 11 of group 10, the second inputs of which are connected to the outputs of the memory block 3, the inputs of which are It is connected to the outputs of register 2 and the second inputs of the inputs of elements 7 of group 6. The outputs of memory block 4 are connected to a group of inputs 16 of counter 5, input 17 of which is connected to the output of pulse generator 8, whose input is connected to output of element 9. Clock output 13 pulses connected to the input 18 of the element 14, the output of which is connected to the input 19 of the register 1, with the input 20 of the register

2 with input 21 of counter 5, the output of which is connected to input 22 of element 12, group of inputs 23 of which is connected to outputs of group 10, and the output of element 12 is connected to input 24 of element 14 and is an output of the device. The binary vector of signs of the situation from the discrete sensors of the control object is fed to a group of inputs 25 of register 1.

The device is configured for a specific system by loading into blocks

3 and 4 for each state of the controlled system of the transitional invariant and a code characterizing the maximum time the system is in this state, respectively. The transition invariant is a binary vector containing units in those bits whose contents in the state codes do not change when moving to any of the allowed states. The zero code is loaded into the zero cell of the memory block 3 (i.e. the first state of the monitored system is always valid). The initial state of both registers is zero. Counter 5 is loaded with a code providing low potential at its output.

The device works as follows.

Slice (differential from high to low) of the first clock pulse, register 1 will write the current state code to the input group 25 of the register from the monitored system, and register 2 to the previous register code 1, i.e. zero, after which the output of the element 9 by Vits mismatch, which will start the driver 8 pulses. As a result, the code corresponding to the maximum time spent by the system in the state whose code is on register 1 will be loaded into counter 5. For each next clock pulse, the contents of the counter change, the code stored on register 1 is rewritten to register 2, and register 1 records a new status code. On elements 7 of group b, the codes recorded on registers 1 and 2 are compared. If they match, then there is no change in the mode of operation of the device. This continues until a change in the state of the monitored system occurs or the output of the counter 5 does not receive a high level signal. The latter, arriving at the input 22 of the element. Establishes a zero potential at its output, which signals the abnormal functioning of the system. In the case of a mismatch of codes recorded on registers 1 and 2 (changing the state of the system), a high level signal appears at the outputs of elements 7 of group 6, corresponding to the changed bits, which through element 9 enters the input of the imaging unit 8 pulses. As a result, the code corresponding to the new state of the controlled system will be loaded into counter 5. At the same time, the error signals from the outputs of elements 7 of group 6 are fed to the first inputs of the corresponding elements 11 of group 10, the second inputs of which receive a transitional invariant selected from memory block 3 at the address recorded in register 2. Thus, elements 11 group 10 checks the validity condition of the given state transition. If there is an unacceptable change of state in the monitored system, then a low level signal appears at the output of block 12, blocking the passage of pulses through element 14 and reporting abnormal operation of the system. Analyzing the contents of the registers allows you to determine the nature

faults occurring in the system.

Blocks 1-3, 6, 10, and 13 are elements of the prototype, and their functionality, as well as the number of inputs and outputs, remain unchanged.

Block 4 is similar to block 3 of the prototype.

Block 5 is a counter with the possibility of parallel loading and can be performed on the basis of integrated circuits, for example, the K155 series.

The shaper 8 pulses can be performed on the basis of integrated circuits, for example, K155AG1.

Blocks 12 and 14 are known elements of discrete technology and can be

made on the basis of integrated circuits.

F o rumlula and z o breetn

A device for monitoring the states of complex dynamic systems containing the first and second registers, the group of elements COMPLEX ON MODULE TWO, the first block of the memory of standards, the group of elements AND, the clock generator, the element OR, and the information inputs of the first register are the inputs of the device outputs of the controlled system, and the outputs are connected to

information inputs of the second register and the first inputs of the elements COMPONENT BY MODULE TWO groups, the second inputs of which are connected to the outputs of the second register and the group of address inputs of the first memory block of standards, and the outputs are connected to the inputs of the OR element and the first inputs of the corresponding AND elements of the group, the second the inputs of which are connected to the group of outputs of the first memory block of standards, characterized in that, in order to expand the functionality of the device by providing the possibility of fixing parametric faults in the elements of a complex system, a second block of standards memory, a counter, a pulse shaper, an AND element and an IL-AND element, the first input of which is connected to the counter overflow output and the remaining inputs to the outputs of the AND elements

group, the output of the element OR is connected to the input of the pulse generator, the output of which is connected to the control input of the parallel loading of the counter, the setup inputs of which are connected to the outputs of the second memory module of the standards, address

the inputs of which are connected to the outputs of the first register, the output of the OR-NOT element, which is the output of the device, is connected to the first input of the AND element, the second input

which is connected to the output of the clock, and the output is connected to the clock inputs of the first and second registers and the counting input of the counter.

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Claims (1)

Claim A device for monitoring the states of complex dynamic systems, containing the first and second registers, a group of elements MODULE TWO, the first memory block of standards, a group of elements AND, a clock generator, OR element, and the information inputs of the first register are inputs of the device for connecting the outputs of the controlled system , and the outputs are connected to the information inputs of the second register and the first inputs of the elements MODULE ADDING TWO groups, the second inputs of which are connected with the outputs of the second register and groups oh the address inputs of the first memory unit of the standards, and the outputs are connected to the inputs of the OR element and the first inputs of the corresponding elements AND groups, the second inputs of which are connected to the output group of the first memory unit of the standards, characterized in that, in order to expand the functionality of the device by making it possible fixing parametric failures of elements of a complex system, a second block of standards memory, a counter, a pulse shaper, an AND element and an OR-NOT element, the first input of which is connected to the output, are introduced into it counter overflow house, and other inputs - with outputs of elements AND groups, the output of the OR element connected to the input of the pulse shaper, the output of which is connected to the control input of the parallel counter download, the installation inputs of which are connected to the outputs of the second memory block of standards, the address inputs of which are connected to the outputs the first register, the output of the OR-HE element, which is the output of the device, is connected to the first input of the And element, the second input of which is connected to the output of the clock generator, and the output is connected to clock cycles the first inputs of the first and second registers and the counting input of the counter.