SU1711178A1 - Data communication system simulation device - Google Patents

Abstract

The invention relates to a data transmission technique and a digital computer. The purpose of the invention is to expand the functionality of the device by simulating the phasing mode when the number of lost messages exceeds the last phase value. The device contains a generator of a random stream of transmitted message pulses, a pulse counter, a group of channels for simulating the transmission of information, and in each channel a generator of random interference pulses for transmitting messages, a generator of random interference pulses for transmitting receipts, a reversible counter for the length of the queue of transmitted messages, triggers, a clock pulse generator , message retry time counter, OR elements, AND elements, receipt counter, transmitted by the slave station, half counter received receipts, count of backflow lost due to buffer overflow, counter of repetition of messages, counter of the number of messages transmitted by the slave station, counter of the number of lost messages, phasing time counter, counter of phasing cycles, register of permissible number of lost messages, comparison circuit . 1 il. (Ls

Description

The invention relates to a data transmission technique and digital computer technology and can be used in the development and simulation of data transmission systems.

The purpose of the invention is to expand the functionality of the device by providing a simulation of the phasing mode when the number of lost messages exceeds the threshold value after the last phasing.

The drawing shows the scheme of the device.

The device contains a generator of 1 random stream of transmitted message pulses, a counter of 2 pulses and a group of 3 channels for simulating information transmission, and in each channel a generator of 4 random pulses of interference in the transmission of messages, the first element is NOT 5, the first element is AND 6, the counter is 7 receipts transmitted by the slave station , the second element is NOT 8, the second element is AND 9, the counter 10 received receipts (by the central station), the generator 11 random interference pulses when transmitting receipts, the counter 12 lost quotes (due to buffer overflow) , the sixth 13 and the seventh 14 elements And, the reversible counter 15 of the length of the queue of transmitted messages, the second trigger 16, the fifth element And 17, the first trigger 18, the third element And 19, the first element OR 20, the fourth element And 21, the generator 22 clock pulses , counter 23 of repetition time

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with

message transmission, the second element OR 24, the counter 25 messages sent to the subordinate station, the counter 26 message repetitions, the eighth 27, the ninth 28, the twelfth 29 and the tenth 30 elements And, the counter 31 lost messages, the counter 32 phasing time, the third trigger 33, the eleventh element AND 34, a counter of 35 cycles of phasing, a counter of 36 pulses, a register 37 of an allowable number of lost messages, a comparison circuit 38, a third 39 and a fourth 40 OR elements.

The device works as follows.

At the initial moment of time, all the counters and triggers of the device are in the zero state, the allowable number of corrupted (lost) messages is written to register 37. Generator 1 generates, at random times, pulses that arrive at counter 2, as well as the inputs of elements 13 and 14 of all channels for modeling information transmission, simulating data flow from the central station to all slaves.

The first of the pulses through the element AND 13, open zero potential, applied to the inverse input from the output of the trigger 18, enters the input of the element OR 20 and the input of the trigger 18, sets it to the unit state. A single potential from the output of the trigger 18 prohibits the passage of pulses through element 13 and allows them to pass through element 14 and element 27 opened by a zero potential applied to the inverse input from the overflow output of the reversing counter 15 of the queue of transmitted messages to the summing input of counter 15 to the model, filling the buffer of the data transmission channel, and to the single input of the trigger 16. The first pulse arriving at the single input of the trigger 1.6 sets it to the single state, and the subsequent pulses do not change Are of this state.

The pulse from the output of the element OR 20 is fed to the input of the generator start 22 clocks, and through the element OR 24 to the counter input 25 messages transmitted by the slave station to the input of the element And 6 and the input of the element 34. The generator 22 clock pulses with counter 23 time message repetitions are designed to simulate time, wait for a receipt for transmitted data, and with a phasing time counter 32 to simulate the duration of the time interval of the phasing process for a particular type of equipment. Clock pulses are input to the counter

23 and to the input of the element 30, which is closed by a zero potential, supplied from the output of the trigger 33. If there is no receipt for a period of time determined by the frequency of the generator 22 and the counter size 23, the overflow pulse from the output of the counter 23 flows through the element 29, open zero potential applied to the inverse input from the output of the trigger 33, to the input of the counter 26 repetitions of messages and through the element OR 24 on, the input of the element AND 6, the input of the counter 25 and the input of the element AND 34, simulating a retransmission of the message to the communication channel. With the subsequent absence of a receipt (except for the moments of time when the data transmission system is in the phasing mode), the procedure is repeated, since the generator 22 and the counter 23 are reset only with a pulse that simulates the transfer of the receipt from the output of the And 9 element.

The generator 4, when transmitting messages with the element HE 5, element AND 6, is intended for modeling error streams,

5 arising in the communication channel during data transmission from the central station to all subordinates.

In the absence of a pulse at the generator output 4, the element 6 and 6 opens and transmits pulses to the input of the element 9, the counter input 7 receipts transmitted by the slave station, the input element OR 40. Thus, the correct reception of the message is simulated, a receipt is issued

5 of the slave station to the central one and the counter 31 is reset. At random times, the input of the HE element 5 from the output of the generator 4 is given control signals that prohibit the passage of pulses through the AND 6 element and allow the pulses to pass through the AND 34 element. distortion (loss) of the message in the process of its transmission over the communication channel (from the central station to the subordinates) and counting the number of distorted (lost) messages.

Simulation of the transfer of the data transmission system to the phasing mode is carried out in two cases.

In the first, when, after the previous (last) phase of the phasing, the sequence of M messages transmitted by the central station to the slaves is distorted. In this case, the output

5, the counter 31 appears an overflow pulse, which, entering through the IL-39 element 39 at the input of the trigger 33, sets the latter in one state. The same pulse, arriving at the installation input of the counter 36, zeroed it.

In the second, when the number of distorted (lost) messages from the total amount transmitted by the central station to slaves after the previous (last) phase of the phasing exceeds a certain threshold value. In this case, the output of the Comparison circuit 38 shows a signal which, arriving through the OR element 39 at the input of the trigger 33, sets the latter to the one state. The same impulse through the OR element 39 has zeroed the counter 36. In addition, the counter 31 is reset to the zero state also by each correctly received message, i.e. impulse from the output of the element And 6 through the element OR 40. The unit potential from the output of the trigger 33 prohibits the passage of pulses from the counter 23 through the element And 29 and permits the passage of pulses through the element 30 to the counting input of the counter 32 of the phasing time.

The duration of the phasing time interval is determined by the corresponding generator frequency 22 and the digit size of the counter 32. The overflow pulse from the output of the counter 32 sets the trigger 33 to the zero state, and also enters the input of the counter 35 of the phasing cycles. The zero potential from the output of the trigger 33 closes the element And 30 and opens the element And 29.

Thus, the output of the data transmission system from the phasing mode is simulated.

The generator 11 of the random pulses of interference in the transmission of receipts with the element is NOT 8, the element And 9 is intended to simulate the distortion (loss) of receipts from the subordinate stations to the central one. At random times from the output of the generator 11 through the element NOT 8 to the input of the element And 9 signals are sent that cover the element And 9 and do not transmit pulses from the element 6. In this way, the distortion (loss) of receipts from the subordinate stations to the central one is simulated. If there are no pulses at the output of generator 11, then pulses from the output of element And 6 pass through element And 9. Thus, the correct receipt of receipts from subordinate stations to the central one is simulated.

Pulses from the output of the element And 9, simulating the transfer of receipts in the reverse channel, reset the counter 23 and generator 22, and also arrive at the input of the counter 10 received receipts and to the subtracting input of the counter 15 through the element 17, which is opened by the potential supplied from the output of the trigger 16 set to one at the time of the start of the data link buffer modeling.

The same potential from the output of the trigger 16 is open element And 21, through which the pulses from the output element And 9 arrive at the input of the element OR 20 and then into the device, simulating the output from the buffer to the channel of the next data block.

At the same time, the contents of the counter 15 are reduced by one. If, with the arrival of the next pulse, the contents of the counter 15 become equal to zero, then from its zero output, the zero impulse arrives at the input of the trigger 16, which sets the trigger 16 to the zero state. At that, elements 17 and 21 close and element 19 opens. An impulse simulating the transfer of receipts from an output of element 9 9 passes through element 19 of the input of the trigger 18 and sets it to the zero state, thus preparing the passage of the next impulse transmitted message directly to the data transmission channel through the element And 13.

In case of overflow of the counter 15, a single potential from its overflow exit prohibits the passage of the next order through And 27 and opens And 28 for counting 12 lost orders with the counter.

Pulse counter 2 is designed to count the number of messages transmitted by the central station, counters 7 and 10 calculate the number of receipts transmitted by the slave station and received by the central station respectively, counter 12 counts the number of requests lost due to buffer overflow, counter 25 is the number of messages sent to the slave station, counter 26 — the number of message repetitions, counter 35 — the number of phasing cycles, counter 37 — the number of corrupted (lost) messages by the slave stations after the previous (last) phasing cycle.

Claims (1)

Invention Formula A device for simulating data transmission systems, comprising a generator of a random stream of transmitted message pulses, a pulse counter and a group of information transmission simulation channels, each of which contains a message repetition counter, serially connected generator of random impulses for transmitting messages, the first element and the first element, AND, the output of which is connected to the counting input of the counter of receipts transmitted by the slave station, serially connected oscillator random noise interference when transmitting receipts, the second element is NOT and the second element is And another input is connected to the output of the first element And the output of the second element And with the counting input of the received receipts counter, the installation input of the message transmission time counter, the installation input of the clock pulse generator, the forward input of the third element And and the first inputs of the fourth and last elements And, the output of the third element And is connected to the zero input of the first t igger, the direct output of which is connected to the inverted input of the sixth And element and the first input of the seventh And element, the output of which is connected to the single input of the second trigger, the forward input of the eighth I / I element and the first input of the ninth And element, whose output is connected to the counting the input of the counter of the lost order, the output of the sixth element AND is connected to the single input of the first trigger and the first input of the first OR element, the second input of which is connected to the output of the fourth AND element, the output of the first OR element - to the first input of the second the OR element and the clock pulse start input, the output of which is connected to the counting input of the message retry time counter and the first input of the tenth AND element, the output of the second OR element, is connected to the counting input of the message counter transmitted by the slave station, the first input of the eleventh AND element another input of the first element And, the output of the fifth element And is connected to the subtractive input of the reversible counter of the length of the queue of transmitted messages, the zero output of which is connected to the zero input the second trigger, the direct output of which is connected to the second inputs of the fifth and fourth And elements and the inverse input of the third And element, the overflow output of the reversible counter of the queue length of the transmitted messages is connected to the second input of the ninth And element and the inverted input of the eighth And element, the output of which is connected to the summing input of the reversible counter of the queue length of the transmitted messages, the output of the overflow counter of the retransmission time of the Messages is connected to the direct input of the twelfth element AND, the output otorrhea coupled with the counting input of the message repeat counter and the second input of the second element OR, the second input of the eleventh element I is connected to the output of the random noise interference pulse generator when transmitting messages, the output of the eleventh element I is connected to the counting input of the counter of lost messages, the direct output of the third trigger is inverted the twelfth element and and the input of the tenth And element, the output of which is connected to the counting input of the phasing time counter, the overflow output of which is connected to the zero input of the third trigger and the counting input of the phasing cycle counter, is output of the random pulse generator of the transmitted messages, connected to the counting input of the device’s pulse counter, etc. by the inputs of the sixth and second inputs of the seventh elements AND all channels of information transmission modeling, the output of the eleventh element I is connected to the counting input of the counter Messages, characterized in that, for the purpose of expanding the functionality of the device by providing a simulation of the phasing mode when the number of lost messages exceeds the threshold value after the last phasing; each channel for simulating the transmission of information further contains a pulse counter, a comparison circuit, a register of the allowable number of lost messages, the third and fourth elements OR, and output of the eleventh element, AND is connected to the counting input of the pulse counter, the bit outputs of which are connected respectively to the information first inlets group of the comparison circuit, the information inputs of the second group of which are connected respectively to the bit outputs of the register of the permissible number of lost messages, the output of the More comparison circuit is connected to the first inputs of the fourth and third OR elements, the second input of the third OR element is connected to the overflow output of the lost messages counter , the output of the third element OR - with unit input of the third trigger and the installation input of the pulse counter, the output of the first element AND is connected to the second input of the fourth element OR, the output of which is connected to the installation input counter. lost messages.