SU1702529A1 - Digital-to-analog converter - Google Patents

Description

(21) 4703265/24 (22) 06/08/89 (46) 12.30.91. Bul

(71) Moscow Energy Institute

(72) C. I. Didenko, V. M. Kapustin. S.I. Gordeev, V.V.Ostrovirhee and G.I. Yakovlev (53) 681.325 (088.8)

(56) USSR Copyright Certificate No. 1064453, cl. H 03 M 1/66, 1981.

USSR Author's Certificate No. 1473084, cl. H 03 M 1/66, 1987.

(54) DIGITAL CONVERTER

(57) The invention relates to automation and computing and can be used in the construction of precision digital-analog information systems. The purpose of the invention is to improve the accuracy of the conversion. The digital-to-analog converter contains the first 1 and second 2 digital-to-analog converters, the adder 3, the subtractor 4, the controlled adder 5, and the control unit 6. Managed adder 5 is made in the form of adder 7 and three devices 8-10 sampling and storage. The introduction of gated feedback from the output of the controlled adder to the inputs of subtractors 4 and adder 3 makes it possible to increase the accuracy of the conversion and eliminate the output signal ripples during transients. 2 h. n. f-ly, 3 ill.

entrance

(L

WITH

3

Yu SL Yu

FIG.

The invention relates to automation and computing and can be used in digital-analog conversion systems and calibrators.

The purpose of the invention is to improve the accuracy of the conversion.

FIG. 1 is a functional diagram of a digital-to-analog converter: FIG. 2 - control unit; in fig. 3 - diagrams explaining his work.

The digital-to-analog converter (Fig. 1) contains the first 1 and second 2 digital-analog converters, adder 3, subtractor 4, controlled adder 5, and block 6 of control. Managed adder 5 is made in the form of adder 7 and three devices 8-10 sampling and storage. The control unit 6 (Fig. 2) is made in the form of five single vibrators 11-15.

Digital to analog converter (Fig. 1) works as follows.

After submitting the converted code to the information inputs of the first 1 and second 2 digital-to-analog converters, a start command is sent to the control unit 6 (if necessary, this command is synchronized with the moment of the code being converted) (Fig. 2. b). On a Start command, the device is reset: the first 9 and second 10 of the sampling and storage device are transferred to the sampling mode, and the third sampling and storage device 8 is placed in the storage mode. In this case, the output of the first digital-to-analog converter (DAC) 1 produces a signal equal to

Ui Nqi -f Ai. where N is the convertible code;

qi is the weight of the least significant bit of the first DAC 1;

Ai - the error of the first DAC 1.

At the output of the second DAC 2, a signal is generated

1) 2 NQ2 4- D.

where Q2 is the low-order weight of the second DAC 2;

Yes - DAC error 2.

At the same time, at the outputs of the adder 3 and the subtractor 4 (for the case when the previous value of the converted code is O, i.e. the voltage at the output of the controlled adder 5 is 0), the signals will be respectively

from Nq2 4- Az + Dz;

(Ui-U3) + A4,

. Where AZ, A - errors of the adder 3 and subtractor 4, respectively, and transfer coefficients of the subtractor on all inputs

accept equal K / 2. The voltage U4, as commanded from the third output of the control unit 6 (Fig. 2c), is stored in the first sampling and storage device 9 (VHF). Then on command to second exit

control unit 6 (Fig. 2d), the first DAC 1 changes its internal state and the error of its output signal changes sign, i.e. Ui Nqi-Ai. With

this output of the subtractor 4 signal paI / vein UV -2 (Ui - Oz) + AI. This signal

on command from the fourth output of control unit 6 (Fig. 2e) is recorded in the second OUT section 10, and at the output of adder 7, a signal U is generated by ts + A /, where L is the error of adder 7. The voltage U on command from the first output of block 6 control (Fig. 2e) is recorded in the third

VHD 8. This ends the cycle of forming the output signal of the digital-to-analog converter, which is equal to or UBb. 2 A / K + -t-At / K.

From the last expression it can be seen that the total conversion error in this technical solution is less than the error of the prototype device by the error value of the adder 3.

upon receipt of the next signal, the Start voltage from the output of the third VHR 8 goes directly to the second summing input of the subtractor 4, and through the adder 3 to the subtracting input of the subtractor.

as a result, in the output signal of the subtractor 4, the component U is absent, which leads to the independence of the output signal of the entire device as a whole from the previous value of the signal at the output of the controlled

adder 5. For the same reason, there is no accumulation of conversion error and, unlike the prototype, there is no output ripple in the output signal during transients. At that

At the same time, with repeated Start commands, the conversion error due to the phenomenon of self discharge by the water economy department decreases.

Controlled signals are generated in

control unit 6 using five single-vibrators (Fig. 2a). The Start command enters the inputs of the first four one-shot 11-14. At the outputs of the first three. Single vibration 11-13 are formed

control commands for the first VHR 9, the first DAC 1 and the second. OIL 10, respectively. The third UHF 8 control command is generated at the output of the fifth one-shot 15. The single-shot 14 triggered with a certain delay. The pulse durations at the outputs of the one-shot are selected taking into account the duration of transients in the units of the device.

Claims (3)

Claim 1. A digital-to-analog converter containing a first digital-to-analog converter, the information inputs of which are combined with the corresponding information inputs of the second digital-analog converter, are the input information bus, and the output is connected to the first summing input of the subtractor, the output of which is connected to the information input of a controlled adder The output of which is connected to the first input of the adder, the second input of which is connected to the output of the second digital-to-analog conversion The output is the output bus, the first control input of the controlled adder is connected to the first output of the control unit, the second output of which is connected to the control input of the first digital-to-analog converter, characterized in that, in order to increase the accuracy of the conversion, the subtracting and second summing the inputs of the subtractor are connected respectively with the output of the adder and with the output of the controlled adder, the second and third control inputs of the last of which are connected respectively with the third and fourth outputs of the block Single control, the input of which is an input bus Start. 2. The transducer according to claim 1. about tl and h a yu and and so. what controlled adder configured as an adder and three sampling and storage devices; the information input of the first sampling and storage device is connected to the information input of the second sampling and storage device; and is the information input of the controlled adder; the outputs of the first and second sampling and storage devices are connected respectively to the first and second the inputs of the adder, the output of which is connected to the information input of the third sampling and storage device, the output of which is the output of the controlled adder, the control inputs of the first first, second and third the sampling and storage devices are respectively the second, third, and first control outputs of the controlled adder. 3. The transducer according to claim 1, of which is that the control unit is made in the form of five one-shot, the input of the first one-shot is combined with the inputs of the second, third and fourth one-shot and is the input of the block, the output of the fourth a one-shot is connected to the input of a fifth one-shot, the output of which is the first output of the unit; the outputs of the first, second and third one-shot are respectively the third, second and fourth block output. FIG. 2 Start IF at one Fig.Z