SU1691816A1 - Apparatus for measuring short time intervals - Google Patents

Abstract

The invention relates to a measurement technique and can be used as interpolation blocks in time-to-code converters. The meter contains triggers 4, 5, key 9, controlled generators 10, 11 of current, comparator 13. element 6, accumulator capacitor 18, pulse counter 23. Sources 1, 2, 3 of the reference voltage, triggers 6, 7, 8, controlled current generator 12, comparators 14, 15, element 17, gated drivers 19, gated 20 inverters, lines 21, 22 delays. 2 Il.

Description

Sc 18

CA15

2

Claims (1)

Claim A short time meter comprising a common bus, Start and Stop signal buses, a timing bus, a voltage reference bus, two triggers, a key, two controllable current generators, a storage capacitor, a comparator, an I circuit, and a pulse counter, and the Start input bus being connected to With the input of the first trigger, the output of which is connected to the key input, the first output of the key is connected to a common bus, the inverse output of the second trigger is connected to the control input of the first current generator, the output of which is connected to the output m of the second current generator, with the second key output, the inverse input of the first comparator and the first lining of the storage capacitor, the second lining of which is connected to a common bus, the direct input of the first comparator is connected to the first bus of the reference voltage, the bus of the timing sequence is connected to the second input of circuit I, output which is connected to the counting input of the pulse counter, characterized in that, in order to increase the speed of the meter, three triggers are introduced into it, controlled by ge169 1816 current keragor, two comparators, Scheme I. two delay lines, gated drivers with three states at the output and gated inverters with booming states at the output, input bus for bringing the device to its initial state Soros, output bus Zatros information output buses and two opera voltage buses, the input bus Stop through the first delay line is connected * 0 with the inputs of the second and third triggers, the direct output of the second trigger is connected to the first input of the circuit AND, the inverse output of the third trigger is connected to the control input of the second generator Single and direct -5 output - to the input of a third current generator control output of which is connected with the first electrode of the storage capacitor and the direct inputs', second and third comparator inverted input 20 which is connected to the second and. the third voltage reference bus, respectively: - p. the direct output of the first comparator is connected to the first input of the circuit I. The direct output of the second comparator is connected to the C-input 25 of the fourth three ;; yep. whose inverse output is connected to the second input of the circuit I. The output of which is connected to the R-inputs of the first. of the second and gray triggers, with the C-input of the fifth trigger, the inverse output of the fifth trigger is connected to the {inputs of the first and second triggers, and through the second delay line to the output bus of the request, the input reset bus is connected to the R-inputs of the fourth and fifth • • diggers, the third input of the And circuit and the R-input of the pulse counter, the outputs of which are bitwise connected to the information inputs of the gate drivers and inverters, the outputs of which are bitwise combined and fed to the output information buses, the direct output of the third comparator By connecting the third -Log triper and strobe shaper gated entry inverse output of the third comparator is connected with a strobe input of the gated inverter on Kvhody all triggers ON signal is applied, and on -Log {fourth and fifth signal 1 triggers. Start q SP7OP jf 5T ΙΠί in hChGL -1 <· -h Llr - ^ 3 .FROM'*;, / s' X- cPs GA 15 Ρ1δ .......... G ' τ £ / S 1. -IN-.....-..........-