SU1676094A1 - Counting device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices controlling and controlling computer technology. The aim of the invention is to extend the functionality of the issuance of codes. The counting device contains counter 1. register 2, first 3 and second 4 triggers, blocks 5 and 6 of the sample codes, inverters 7 and 8, and elements 9 and 10 of coincidence. The goal is achieved by introducing trigger 4, code selection blocks 5, and inverter 8. 2 epfl, 3 ill.

Description

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The invention relates to a pulse technique and can be used in devices controlling and controlling computer technology.

The aim of the invention is to extend the functionality of the issuance of codes.

Figure 1 shows the structural diagram of the counting device; Figures 2 and 3 are embodiments of a code selection block.

The device contains a counter 1, a register 2, the first 3 and second 4 triggers, the first 5 and second 6 code selection blocks, the first 7 and second inverters, the first 9 and second 10 match elements, the first input 11 of the counting device, the second input 12 of the counting device and Outputs 13 counters. Blocks 5 and 6 contain a decoder 14 or reference element 15 and bus 16 codes. Input 11 is connected to the counting input of the counter 1 and through the inverter 7, the element 10 coincidence - to the clock input of the register 2, the outputs of which are connected to the outputs 13.

The information inputs of register 2 and blocks 5 and 6 are connected to the outputs of counter 1. Input 12 is connected to the counting input of trigger 3, the reset input of which through inverter 8 is connected to the output of block 5. Control input of block 5 is connected to the input of matching element 10 and directly trigger output 4. The output of block 6 is connected to the input of coincidence element 9, the control input to the inverse output of trigger 4. The installation input of trigger 4 is connected to the inverse output of coincidence element 9, whose second input is connected to the reset inputs of trigger 4 and 2 and exit three gery 3.

The device works as follows.

In the initial state at input 12, the input signal is absent (there is a zero level). Trigger 3 is in the zero state. In this case, the zero level of the trigger output 3 blocks the coincidence element 9, sets a unit level at its inverse output, keeps the reset trigger 4 and the register 2 at the input state in the zero state. The zero level of the direct output of the trigger 4 keeps zero levels on the outputs of block 5 and element 10. At the output of the inverter 8 - a single level that permits trigger 3 to receive input signals. At outputs 13 - zero code (zero levels). At input 11 there are clock pulses that are inverted by inverter 7. Counter 1 recalculates clock pulses

input 11. On the leading edge of each clock pulse, the contents of counter 1 are incremented by one.

Block 6 periodically highlights on

its output pulses with a duration equal to a period of clock pulses and a repetition frequency equal to the product of the conversion factor of counter 1 to the period of the clock pulses. The device is in the initial state until input signal 12 is received. On the leading edge of the input signal, the trigger 3 is set to one. When reaching the counter

5 1 of the code, which is selected by block 6, the trigger 4 is set to one. The zero level of the inverse output of the trigger 4 overlaps the block 6. The single level of the direct output of the trigger 4

0 unlocks block 5 and match item 10. At the end of the clock pulse of input 11, the counter 1 rewrites its contents into register 2, which is fed to outputs 13. On the latter, codes are allocated, starting with

5 of the code selected by block 6. When counter 1 reaches the code selected by block 5, the device elements are set to the initial state. The next input signal repeats the process. The time spent by the code on the outputs 13 takes the period of the clock pulses.

Thus, by changing the choice of codes in blocks 6 and 5, it is possible to change both the initial selectable code and the number of codes. The device operates with input signals of input 12 of any duration, the minimum duration determined by the response time of trigger 3.

Claims (3)

1. A scaling device containing a counter, a register, a first trigger, a first and a second match elements, and a first inverter, whose input is connected to the first 5 by the input of the counting device and the input of the counter, the outputs of which are connected to the information inputs of the register, characterized in that, in order to expand the functionality of the output of the codes, a second trigger, a second inverter, the first and second code selection blocks, the information inputs of which are connected to the outputs, are entered meter, control inputs - to the output and the inverse output of the second 5 flip-flops, the setup input of which is connected to the inverse output of the first coincidence element, the first input of which is connected to the output of the second code selection block, the second input to the output of the first trigger, the reset input of the second trigger and the reset input of the register, the outputs of which are connected to the outputs of the counting device, clock input - to the output of the second coincidence element, the first input of which is connected to the output of the first inverter, the second input to the output of the second trigger, the output of the first code selection block through the second inverter is connected to move the first latch reset, the count input of which is connected to the second input of scaler. 2. The device pop. 1, characterized in that the block selection code contains 51 S2 §I Cri FIG. g the decoder, information inputs, the control input and the output of which are connected respectively to the information inputs of the block, the control input of the block and the output of the block. 3. Device pop.1, characterized in that the code selection block contains a comparison element, the first inputs of which are connected to the information inputs of the block, the second inputs to the code buses, the control input to the control input of the block, output to the output block. sixteen {; 15 Fig.Z