SU1621154A1 - Clocking device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to expand the functionality by converting information words synchronized by leading or lagging clock pulses into information words synchronized by clock pulses coinciding with them, is achieved by introducing the third element OR 5, second trigger 2, bus 15 , the second output bus 17, the Device also contains the first trigger 1, the first, second elements OR 3.4, the element And 6, the counter 7 pulses, the element 8 delay, the imager 9 pulse a, 10 bus clock, the control bus 11, the conversion factor in line 12 us.anovki O input bus 13, a first output bus 14, bus 16 impupsov account yl 3

Description

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Claims (1)

Claim A synchronization device containing a first trigger, the S-input of which is connected to the clock bus, the first 30 Figure 2 OR element, the first input of which is connected to the installation bus at 0 ”, the output is with the input of the delay element, the second OR element, element And, pulse shaper, pulse counter, the control input of which is connected to the control bus, conversion factor, input bus , pulse counting bus, a first output bus, characterized in that, for the purpose of 10 expanding the functionality. the mode bus, the second output bus, the third OR element, the second trigger, the direct output of which is connected to the first output bus, the S-input with 15 input bus, the R-input with the output of the delay element and with the R-input of the first trigger, are introduced into it the inverse output of which is connected to the reset input of the pulse counter, the output of which. connected to the pulse shaper, the counting input - with the output of the third OR element, the first input of which is connected to the count pulse bus, the second input - with the mode bus and the first input of the And element, the second input of which is connected 25 to the clock pulse, the output - with the first and the second inputs of the second and first OR elements, the second and third inputs of which are connected to the output of the pulse shaper, and the output of the second OR element is connected to the second output bus. FIG. b