SU1675911A1 - Partial derivatives differential equations solver - Google Patents

Abstract

The invention relates to analog-to-digital computing and is intended to solve partial differential equations. The purpose of the invention is to increase device speed and accuracy. To achieve the goal, a tabular method of calculating the optimal reference voltage and scale factor is used, continuous hardware monitoring of the R-grid overvoltage and the automatic scaling system is performed, and the end of the transition process is reliably and unambiguously fixed in the grid electric model by introducing into the device a comparator, blocks of the permanent memory and a trigger, and in the disturbance control unit it will The variable has a variable component and zero discriminators with corresponding connections. 4 il.

Description

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The invention relates to analog-to-digital computing and is intended to solve partial differential equations.

The aim of the invention is to improve device performance and accuracy.

FIG. Figure 1 shows a block diagram of a device for solving partial differential equations; in fig. 2 and 3 are timing diagrams explaining the operation of the perturbation control node for different characters of the transition process in the R-grid; in fig. 4 - the algorithm of the proposed device.

The device for solving differential equations in partial derivatives contains R-grid 1, converter 2 voltage - current, converter 3 code-voltage, memory block 4, digital-to-analog converter 5 (DAC), comparison block 6, analog-to-digital converter (ADC ) 7, comparator 8, differentiator 9, variable component amplifier 10, register 11, first element 12, second discriminator 13 zero, first discriminator 14 zero, second element 15, fixed memory unit 16, encoder 17, block 18 memory, the first block of elements And 19, the second And the block elements 20, the first 21 and second 22 display units, OR gate 23 and trigger 24.

The device works as follows.

In the memory block 4, the array of initial data for 3 is entered. The grid electric model R-grid 1 is configured according to the problem to be solved. To start the device at the same time to reset the register

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11 and the reset input of the trigger 24 is given a pulse, which sets them to the zero state. The zero code from register 11 goes to the address inputs of blocks 16 and 18 of the permanent memory. At the zero address of the first block of the permanent memory. At the zero address of the first block of the direct memory, such a control code of the digital-to-analog converter (DAC) 5 is flashed, which corresponds to the initial minimum output voltage of the DAC 5, which is the minimum reference voltage Uon.min of the converter 3 code - voltage. At the outputs of converter 3, the code is voltage and voltage converter 2, the current is set to the minimum initial voltages and currents proportional to the codes of the source data recorded in memory block A and the reference voltage. On the R-grid 1, the potential distribution is formed, the comparison unit 6 continuously selects the maximum absolute value potential I Uj max I of the nodal points of the R-grid 1. The maximum component I Uyax I of the vector of nodal potentials thus generated is fed to the input of the node control of disturbances, the input of the ADC 7 and the input of the overvoltage comparator 8, which continuously compares I UiMasc I with the maximum voltage on the R-grid. In case Shyaks imax comparator 8 generates a signal indicating the presence of overvoltage on the R-grid 1, which through the first element And 12 enters the input of the encoder 17 only when the disturbance control node issues a level of the end of the transient process which the encoder 17 generates on the fourth output a signal that triggers the A / D converter 7, and on the third output of the device an information signal. The initial scale is incorrect, indicating the need for recalculation of the original data. A / D converter 7 performs I 1 conversion. 1) 1 max I to a code that is written to register 11 by readiness signal from A / D converter 7. The code equivalent of I UiMaicc I recorded in register 11 is the address for entering blocks 16 and 18 of the fixed memory. those implemented on the 556РТ7 microcircuits. In block 16 of the permanent protection of protection, the values of the optimal control codes of the digital-to-analog converter (D / A converter) 5 and information bits (flags) are fed to the corresponding inputs of the encoder 17 and participate in shaping the output signals of the device, In this case, since UjMaKc (KI iMax, NE INPUT DAC 5 is issued a zero control code, which

removes this overvoltage. The signal Initial scale is incorrect through the element OR 23 cocks the trigger 24, resolving through the second and first blocks of the elements AND the indication of the Uon code and I and Max code, respectively (kch recorded in register 11. After evaluating the displayed information, the source data are recalculated and reloaded into block 4 memory, after which the device startup mode is repeated (Fig. 4, blocks 6-9).

If overvoltage is absent, i.e. The IUiM3Kc ISUniaKc, the logic for the further operation of the device, is determined by the fixed memory blocks 16 and 18. The linear relationship between the value of I 1) max I and the value of the reference voltage Don output by the DAC 5, which in the case of unsaturated operation of the elements of the converter 3, saves the code - voltage and converter 2 voltage - current, allows you to calculate and flash blocks 16 in advance and 18 fixed memory so that the measured value of I UIMBKC I to issue the optimal reference voltage codes

U on opt & u on min

and scale factor

IMAX -A I U | (K) max

but

ax - UMakc - A

for which

/ Ui

where A is a certain fixed predetermined small value determined by the technical capabilities of the particular computing system used;

I UiMaKc / I - is maximum in absolute value of the component of the vector of nodal potentials formed on the R-grid at Uon opt, i.e. after a cycle of optimal automatic scaling, at which the absolute in magnitude component of the nodal potentials vector would be close to the limiting operating voltage of the grid element, then the entire range of selected bits is used and the UpK codes of nodal potentials contain the maximum number of significant digits. In the process of modeling on an R-grid at optimal scales, the required number of iterations is reduced due to a better adaptation of the grid element to the problem being solved, as a result of which the device speed and resolution accuracy is improved.

Thus, if 1) ol.mzh Shmaks I Umaks,

Then, in block 18, the computation in tabular fashion and the issuance of the optimal scale factor a are performed, and in block 16 in the permanent memory, computation in tabular fashion of the code of the DAC controls 5 to obtain the optimal reference voltage Don.opt. In addition, in this case, information flags are output from the constant memory block 16 to the corresponding inputs of the encoder 17, which, after receiving a signal about the end of the transient, caused by the input of new currents Uon.opt into the R-grid. outputs the information signal to the first output of the device. The grid is ready, allowing removal from the grid element of the current decision, and in this case,

IUlMaKC (K) 1 11max- AU CODES Uon I, s (I I H6

are displayed (Fig. 9, blocks 10, 11, 17, 18, 19, 20).

(YU

IF 0.5 Uon MHH IUtM8KC KUon.MHH, THEN

The fixed memory block 16 issues a DAC control code 5 for obtaining the maximum reference voltage Osigmaig ymaxCop.min. and information flags arriving at the corresponding inputs of the encoder 17 determine that the corresponding signals are output to the third and second outputs of the device. The grid is ready and the scale is not optimal, indicating that in this case the maximum component is about the limits:

0.5.UMa "IUlMailK) hUvaicc

At the same time, the Scale signal is not optimal through the OR element 23 and cocks the trigger 24, allowing the indication of the codes Uon and lUiManc I, and the digital output of the scale factor of the device contains the code of the maximum scale factor Omaha (Fig. 9, blocks 12. 13, 14, 15, 16) . In this case, the user is given the opportunity to decide on the appropriateness of further calculations at this scale.

If I UIMSKC is 0.5 Uon.min, then the permanent memory block 16 issues information flags to the encoder 17, with which the device generates the output signal of the device. The initial scale is incorrect, allowing the Uon and I codes to display Uon and I Ulmaxc I through blocks 23 and 24. AND TALKING IN

in this case, it is impossible to perform satisfactory scaling (with the available source data) due to finding the nodal potentials on the R-net in the noise zone. The DAC control code is 5, the a code and the Grid signal are not formed. As in the case of the presence of an overvoltage on the R-grid 1, after evaluating the information projected by blocks 21 and 22, it is necessary to recalculate the initial data and recalculate

them in the memory block 4, then repeat the device startup mode (Fig. 9. blocks 12, 8.9),

The perturbation control node consisting

From the differentiator 9, the amplifier of the displaced component 10, the first 14 and the second 13 discriminators zero and the second element I 15, works as follows. Maximum component

Shyax l is supplied in parallel to the variable component amplifier 10 and to the differentiator 9, which outputs a differentiated signal a (UiMaxc Vdt. Next, the occurrence is monitored).

variable component UIMSKC in the zero zone of establishment by means of a two-threshold discriminator 14 zero. Measurement Permission Oyax is issued by a two-threshold discriminator 13

zero at the moments of extrema of the variable component, i.e. when "(UIMBKC. Thus, the second element of AND 15 will give the level of the actual end of the transition process at that point in time when

the signals from the amplifier 10 of the variable component and from the differentiator 9 will enter their zero zones.

Claims (1)

The use in the invention of a tabular method of calculating the optimal cov., S of the reference voltage and scale factor, the implementation of continuous hardware monitoring of overvoltages, as well as the proposed construction of a perturbation control node, which allows to register the moment of the actual end of the transient process, provides the optimal distribution of the nodal potentials on R-grid in each iteration, leading to the maximum adaptation of the grid electric model to the problem being solved for the minimum possible it - during one transient. This leads to an increase in the accuracy of the solution in each iteration, a decrease in their duration, as well as to a reduction in the total number of iterations required, as a result of which the device speed and accuracy of the overall problem solution increases. Invention Formula A device for solving differential equations in partial derivatives, containing an R-grid, a voltage-current converter, a code-voltage converter, a memory block, digital-analogue converter, comparison unit, analog-digital converter, register, first and second elements And, first and second blocks of elements And, the outputs of which are connected respectively to the inputs of the first and the second display unit, the OR element, the generator and the differentiator, the first boundary node of the R-grid is connected to the output of the voltage converter - a current, the first input of which is connected to the first output of the converter code - voltage, the second output of which is connected to the second voltage converter - uk and the second grid unit R of the grid, the central nodes of which are connected to the corresponding inputs of the comparison unit, the twist of which is connected to the input of the analog-cm Spring Converter and the input of the differentiator, the output of the first Lemmata I is connected to the first input of the encoder, the second input of which is connected to the output of the second element I, the input of the iafroaalogo converter is connected to the third input of the encoder, the output of the digital-to-analogue converter is connected to the input of the reference voltage reference of the converter code-voltage, the input of the code The connection is connected to the output of the memory unit, the information input of which is the input of setting the initial data array yci roysgva, characterized in that, in order to improve speed and accuracy, the device is inserted the comparator, the first and second blocks of the constant memory, the trigger, the amplifier of a variable component, the first and second discriminators are zero, the output of the comparison unit is connected to the input of the variable component amplifier and the input of the comparator, the output of which is connected to the first input of the first element And, the second input of which is connected to the output of the second element And, EPA the output of the variable component amplifier is connected to the input of the first discriminator zero, the output of which is connected to the first input of the second element I, the second input of which is connected to the output of the second discriminator zero, whose input is connected to the output of the differentiator, the first output of the encoder is connected to the input of the start of the analog-digital converter , the code output of which is connected to the information input of the register, and the readiness output to the input of the register entry, the zero input of which is connected to the reset input of the trigger and is input device start house, register output is connected to the first input of the first block of elements AND and the address input of the first and second blocks of permanent memory, the output of the first block of permanent memory is connected to the first input of the second block of elements AND to the third input of the encoder, the second and third outputs which are connected respectively to the first and second inputs of the OR element, the output of which is connected to the trigger setup input, the direct output of which is connected to the second inputs of the first and second blocks of AND elements, the second output of the encoder is Device output The scale is not optimal, the third output of the encoder is the output of the device. The similar scale is incorrect, the fourth output of the encoder is the output of the device. The grid is ready, the output of the second fixed memory unit is the output of the device's optimal scale factor. Out long ten 8sh   / ZSttPT 6A 13 G AND Out & l 14 tp Out 5l. 15 And 8sh. 6 / 1.73 ..fiwx.fii.7 Out 6l. 15 t hz - Fm2  t Yag.Z. Gil. (End J