SU1672462A1 - Semantic network processing unit - Google Patents

Abstract

The invention relates to computing and is intended for the construction of multi-microprocessor computing systems for distributed information processing in artificial intelligence systems. The purpose of the invention is to expand the functionality of the processor by ensuring the formation of knowledge bases. The processor comprises a processing unit 1, a memory unit 2, an external memory controller 3, linear adapters 4-7, a command adapter 8, an information register 9, a register of 10 common features. 7 il.

Description

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The invention approaches computer technology and is intended for building multimicroprocessor computer systems for distributed information processing in artificial intelligence systems.

The purpose of the invention is to expand the functionality by ensuring the formation of knowledge bases,

Figure 1-4 shows the structural diagrams of the proposed processor, the command adapter, the information register, the register of common features, respectively; Figures 5-7 show the CPU operation algorithms.

The processor (Fig. 1) includes a processing unit 1, a memory unit 2, an external memory controller 3, linear adapters 4-7, a command adapter 8, an information register 9, a register of 10 features, a common bus 11.

The command adapter 8 (Fig. 2) contains a decoder 12, a response signal generating unit 13, a readiness signal generating unit 14, a serial-parallel converter 15, a key 16, a repeater 17 "

The information register 9 (FIG. 3) contains the address decoder 18 and the shift register 19.

Register 10 common signs contains the decoder 20 addresses and register 21.

The command adapter performs the functions of receiving control requests from the host computer in a sequential code, converting them into a parallel internal operation code, issuing this code for execution to the processing unit, as well as sending external confirmation signals to the external computer to synchronize the operation of unit 1 s other network processors.

The request signals from the host computer through the repeater 17 are fed to the enable input of the node 13 to generate a response signal, which is a D-flip-flop, as well as to the line of the highest priority of the interrupt request on the common bus. On this request, unit 1 interrupts its operation and proceeds to the interrupt handling routine upon the incoming request. The command adapter in the address field of block 1 must occupy the higher address bits. When accessing the command adapter from block 1 of the decryptor

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Torus 12 decrypts the address of the adapter. From the output of the decoder, the signal is fed to the readiness input of the readiness signaling node 14, which is a D-flip-flop, and to the installation input of node 13, from the first output of which the network processor is ready to receive the macro command, and from the second The output to the key 16 is given the enable signal to enable it. In addition, the response signal generation unit 13, the readiness signal generation unit 14 and the key 16 protect the entire multimicroprocessor system from failures of individual network processors, since in case of a malfunctioning of the latter, they are automatically disconnected from the control buses of the host computer by removing the failing unit 1 processing.

During normal operation, the macro in a sequential code from the host computer through the key 16 is fed to a serial-parallel converter 15, which is a shift register, when filled, the input of the node 13 and the readiness input of the node 14 is received, the latter informs the external computer completion of the reception of the macro, and the processing unit 1 permits the reception of the serial-parallel converter 15 from the outputs of the operation code. The host computer may load data into the shift register 19 or read from it in a sequential code that is the source or the resultant for the processor. The reception and output of external data is carried out by a strobe signal from the host computer. Inside the processor, the register 19 has a parallel output to the common bus and is addressed by the processing unit 1 as an I / O port.

In register 21, the processing unit can independently write two bits of the internal state of the processor. From the output of register 21, these bits arrive at the characteristic lines of the multi-microprocessor system and are analyzed by the host computer during calculations.

The operation of the processor can be illustrated by the example of working with knowledge organized in the form of a pyramidal semantic network (PS).

A pyramid network is a directed graph in which there are no vertices with a degree of approach 1. Vertices of this graph are called elements, and arcs are links. Elements with a 1-degree approach are called associative elements. Elements with an entry degree of 0 are called receptor elements. The inputs of associative elements are called active, if they are associated with the outputs of other associative or receptor elements, and passive - otherwise.

PSs provide an economical, hierarchical and associative storage of knowledge about tasks and environments. When constructing a PS, connections between objects are automatically established by highlighting the intersections of descriptions of objects and entering into the network the elements corresponding to these intersections. PS defines the processes of forming concepts based on inductive learning methods. PSs are convenient for performing associative search operations, as well as such semantic analysis procedures, such as extracting information related to a specific task, recognizing the applicability of action models to situation models, transforming a model of one situation into a model of another situation, etc. (Gladun .P. Planning solutions. Kiev: Naukova Dumka, 1987).

All the above features of PS are determined by the following rules for their construction.

Rule 1. If, when entering a description of a new object in the network, associative elements A appear, having in their subset excited control commands of the control computer

Entering the description of the first object 1 (rule 1 does not work)

Call free cells- Reception of the output command and overload processors for receptors load in the shift register and their numbers should be written in the input / output of the sign of the name of the receptors, the names of the internal RAM.

Translate the receptors in accordance with the description of the object into the excited state by loading the excitation function into the I / O shift register.

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the network is introduced; new elements are the inputs of each of which are connected to the outputs Bj, and the output is connected to one of the passive inputs. New associative elements are in an excited state. After the introduction of new elements in all parts of the network where the condition of rule 1 is fulfilled, rule 2 is fulfilled.

Rule 2. If there are more than one excited element (receptor or associative) in the network that does not have other excited elements in its superset, then a new associative element is added to the network, and its connections are connected to the outputs of the excited elements. The new associative element is in an excited state.

In other words, in the process of fulfilling Rule 1, the network structure is rebuilt by changing the links between the elements and entering the vertex elements of the pyramids corresponding to the intersections of the sets, and in the process of fulfilling Rule 2 the network is completed by integrating the excited elements into the pyramid.

The operation of processors in the composition of a multiprocessor homogeneous computing system when building an MS in accordance with the above rules is as follows. Moreover, it is considered that each processor is a single network element (receptor or associative) with all its connections.

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Read the information from the I / O register and place it in the appropriate area of the internal RAM, which corresponds to the excitation of the receptor processors.

Application of rule 2

Call the free processor under the description of the new object through the input / output shift register and enter its number in the table of element names.

Excite the processor object.

Establish links between the excited elements.

Enter descriptions of subsequent objects. Application of Rule 1

Fill in the table of receptor names for a new description of the object by performing the procedure for finding free cell-processors under the receptors. Excite the receptors.

Spread arousal over logical connections

tons of excited elements, all logically associated with

them network elements. Upon receipt of messages, each object processor will analyze the conditions of its excitability, during which, by returning messages with the command to extinguish the excited elements in its subsets,

Receiving a call command and loading into the I / O shift register of the busy sign from the internal RAM.

Read the information from the I / O register and place it in the appropriate area of the internal RAM, which corresponds to the excitation of the processor object.

To an excited processor object, send via communication channels a message with the command to establish logical connections with it to other excited network elements, which upon receipt of messages create short lists of communications with the processor object in their RG, send it their physical addresses and extinguish their own excitation Upon receipt of the response messages, the processor object in the RAM creates lists of links with the elements of its subset, while remaining excited.

Run the commands of the host computer to identify and excite the receptor elements.

Excited receptor processors send messages

Analyze the condition of the end of the previous command execution by polling the register of common signs of the network. Select the intersection of object descriptions

Analyze the condition of the end of the previous command execution by polling the register of common signs of the network. Go to rule 2.

As can be seen from the considered example, the processors, when working with semantic networks, interact strongly with each other, as well as with the host computer, receiving and executing commands and exchanging data in parallel mode. The flexibility to control the computational process is achieved by obtaining a processor via macro command adapters from the control computer and further autonomous operation of the processor network. Moreover, the progress of the calculations depends on the data loaded via the shift register and, in turn, send the excitation messages over all output logical links or, if they are not, remain in the excited state. Partially excited object processors in the input field label field for fixing that these connections come from the excited elements.

Partially excited communication object processors (1) send messages with the team to search for free processor cells and, upon receiving answers from them with addresses, send messages with lists of excited communications and their address to them. To these new processors, by the received lists of communications, send messages with the command to quench the excited elements and with the command to correct the communication pointers to the newly formed elements. New items are in a state of excitement.

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yes / output. The end of the execution of a macro or the impossibility of completing the calculations is signaled by information at the output of the register of common features.

In known devices (for example, in transputers), such interaction can be organized either by allocating a separate channel, which significantly reduces the communication capabilities of the network, or by organizing the exchange through a common memory field. In the latter case, loss of performance is inevitable,

since it requires a constant interrogation of the memory in order to determine the arrival times of control information or data for processing. Synchronous processing of data arrays in such a network becomes problematic.

The processor's job is to execute programs stored in an external storage device (each network processor has its own memory device), to process interrupt requests from the host computer or to operate under its control, and also to send messages to nearby neighbors via linear adapters. Therefore, it is advisable to consider the algorithm of the network processor in three aspects:

1) information processing

2) work with a leading computer,

3) messaging with neighbors. Information processing includes

interpretation of received messages and commands of the wave language, as well as the organization of the actual computational process. A verbal description of one of the algorithms for working with knowledge is given above.

Figure 4 shows the flowchart of the processor with the host computer, figure 5.6 shows the message exchange algorithms with neighbors, as well as the exchange protocol

Message exchange protocol:

1. Check the channel performance

2. Install the channel.

3. To transfer the service message defining the main one.

4. Answer:

a) ready to receive a message

b) the input buffer is full,

c) have a copy of the message.

5.Transmit the main message in case 4, a.

6. To wait or work with another channel in case 4, b „

7. Cancel a message in this direction in case 4, in,

8. Receive confirmation of receipt of the message in case 5.

9. Disassemble the channel.

In order to reduce the number of external outputs in the processor, information is exchanged with the host computer in a sequential code. The means of converting sequences of bits into an internal parallel code are serial-parallel

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the converter in the command adapter and the shift register input / output.

Information is loaded into the serial-parallel converter in the start-stop mode. Shifts are clocked by pulses with a frequency equal to or a multiple of the processor clock frequency (CCLK). In addition to the command adapter, the CCLK also enters the processing unit and the line adapters. CCLK can be generated both inside the processor and supplied from the outside.

When a network processor operates as part of multiprocessor computing systems consisting of tens of thousands of processors, in view of significant distortions and delays in sending messages at high speeds (over 10 Mbit / s), instead of starting-to-stop synchronization, self-synchronizing may be preferable. codes.

Claims (1)

Invention Formula A processor for processing semantic networks containing a processing unit, an external memory controller, a memory unit and a group of linear adapters whose system inputs and outputs are connected via a common bus, the inputs and outputs of the external memory controller external device being connected to the inputs and outputs of the first group the processor, the inputs and outputs of the external devices of the linear adapters of the group are connected to the inputs and outputs of the second group of the processor, characterized in that, in order to extend the functionality by providing knowledge bases, a command adapter, an information register and a register of common features are entered into it, and their system inputs and outputs of the entered blocks are interconnected via a common bus and connected to the system inputs and outputs of the processing unit, memory block, external memory controller and groups of linear adapters, inputs and outputs of external devices of the command adapter, information register and register of common features are connected to the inputs and outputs of the third, fourth and fifth processor groups, respectively. Interrupt Request Line FIG. 2 Fig.Z FIG. It Re hin oipofo / lki  have a request from y no zvm / Sh. Chlros processing Team lrien I onaffda Bbino HtfWf Team I Request removed I channel selection / Channel operable to set the channel to transmit Jom08f channel y L. Lo Send message i Re8 channel. .i  / I have / le eu & CffoffutfMUD 7 / no end Hem dy  Not / l S Not Mst Mff L. 8rs / № configured. slogan / There are requests 8 X e / 77 channels / Selection and astroan ka / ia / lg rmem Lriem information  N / all requests H Yes about c / 1 already # b / ABOUT FIG. 7  H ABOUT