SU1665365A1 - Device for data display on crt screens - Google Patents

Abstract

The invention relates to automation and computing and can be used to display graphical information from a computer. OBJECT OF THE INVENTION - ENHANCED FIELD OF DEVICES THROUGH THE POSSIBILITY modification period REGENERATION displays information that is achieved by introducing a first element 1 DELAY, AND ELEMENT 4, 6 COUNTER frame pulse, the second element 11 DELAY AND FUNCTIONAL RELATIONSHIPS matching. INVENTION ALLOWS WHEN INCREASING THE VOLUME OF THE DISPLAYED INFORMATION OR THE TIME OF ITS PROCESSING AUTOMATICALLY CHANGE THE PERIOD OF IMAGE REGENERATION. 2 IL.

Description

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About SL SA O SL

The invention relates to automation and computing and can be used to display information from a computer.

The purpose of the invention is to expand the area of application of the device due to the possibility of changing the regeneration period of the displayed information.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the second switch.

The device contains the first delay element 1, the first switch 2, the trigger 3, the AND 4 element, the second switch 5, the frame sync counter 6, the single pulse generator 7, the operational memory unit 8, the address counter 9, the address decoder 10, the second delay element 11 , element OR 12. The diagram denotes information input 13, address input 14, control input 15, clock input 16, synchronous input 17, information output 18, control output 19 of the device and input 20 of the device reset.

The second switch 5 contains a trigger 21 and the element And 22.

The device works as follows.

The information to be displayed on the screen of the cathode ray tube of the vector display is stored in the form of codograms in the RAM block 8. Each codogram is read from the memory block 8 to the output 18 on request at the input 15 of the device. The request forms with a vector display after processing the previous waveform. The processing time of each codogram may differ, therefore the total time of displaying information (image regeneration period) in different cases, for different images is different and in the general case may exceed the period of the frame sync pulses at the input 17 of the device. The address of the next readable codogram in the operating memory block 8 forms the counter 9 of the address. When counter 9 outputs the maximum allowable address, a Log signal is generated at the output of the decoder 10. one.

Pre-information in block 8 of RAM is recorded from input 13. In this case, the address of the record is received at input 14. When the device is turned on by a reset pulse from the input 20, the initial state is set

corresponding blocks.

The frame sync pulse from input 17 through the first delay element 1 and switch 2 sets trigger 3 to

Log G. In this case, the log. 1 is supplied to the first input of the AND 4 element and to the first control input of the second switch 5. At the same time, the supply of the frame clock to the clock input of the counter 6 of the frame clock pulses is blocked by the AND 4 element, because at the moment the frame clock acts, a Log signal is present at the output of the trigger 3. A. If there is a signal A request for information at input 15 of the device, switch 5 provides for the formation of a signal on the generator 7 of single pulses. By the same signal, the address bus of the RAM block 8 is connected to the output of the counter 9 of the address, and the block 8 itself is switched to the information reading mode.

Thus, information from the memory block 8 will be read out, for example, at the first address. The information read signal is a signal from a generator of 7 single pulses, which is fed to the input 19 of the device. On the falling edge of the pulse from the generator 7 single pulses the contents of the counter

9 addresses increased by one. A pulse from the generator of 7 single pulses closes the switch 5, and reading information at the following address of the RAM 8 is only possible with a new request for information on the device input 15, i.e. The operation of the device for retrieving information from the next cell of the RAM unit 8 is repeated.

Suppose that the cycle of information regeneration is shorter than the period of the following sync pulses. In this case, when the address counter 9 is filled, the signal from the address decoder 10 zeroes trigger 3 and the information from the RAM block is terminated before the next frame sync pulse arrives, and the pulse from the decoder

10address confirms the zero state of the counter 6 HR sync pulses.

If the information regeneration cycle exceeds the period of the frame sync pulses, then the second frame sync pulse through the AND 4 element enters the clock input of the counter 6 frame sync pulses and moves it to a state other than zero. In this case, the switch 2 blocks the circuit of the passage of the sync pulse to the input Device. G of the trigger 3. The device waits for the end of the actual information regeneration cycle, and the personnel pulse counter performs the counting of clock sync pulses. At the end of the actual information regeneration cycle, a pulse from address decoder 10 first clears trigger 3 and address counter 9, and then through the first output of second delay element 11 and switch 2 sets trigger 3 again to Log state. 1, after which the same pulse from the second output of the second delay element 11 resets the counter 6 of frame sync pulses, i.e. preparation of the transition to the regeneration cycle with a period equal to the period of the personnel sync pulses, as soon as the regeneration cycle becomes less than the period of the personnel sync pulses.

Thus, the invention allows to monitor the period of the regeneration cycle. If it is less than the period of the personnel sync pulses, then the regeneration cycle is equal to the period of the personnel sync pulses. With an increase in the amount of output information or the time of its reading and playback, the device automatically ensures a minimum regeneration cycle. When the playback time decreases, information automatically switches to a smaller regeneration period.

Claims (1)

The invention is a device for displaying information on the screen of a cathode ray tube. containing the first and second switches, the OR element, the address counter, the address decoder, the trigger, the RAM block, the single pulse generator, the clock input of which is the clock input of the device, the control input of the RAM memory block the input of the second switch is the control input of the device, the output of the RAM block is the information output of the device, the first address input of the RAM block connected to the information input of the address decoder, dklyuchen to the output address counter. the address decoder output is connected to the first input of the device zero trigger, the output of which is connected to the first control input of the second switch, the second control input of which is connected to the output of the OR element, the first input of which is connected to the second input of the device zero trigger, is the input of the device reset pulse, the second address and the information inputs of the RAM are the address and information inputs of the device, respectively, characterized in that, in order to expand the field of application of the device due to the possibility of changing the regeneration period of the displayed information, it contains a frame clock pulse counter, the first and second delay elements, the And element, the first input of which is connected to the trigger output, the input The unit unit of which is connected to the output of the first switch, the first information input of which is connected to the output of the first delay element, input which, connected to the second input of the element AND, is the synchronous input of the device, the output of the element AND is connected to the clock input of the frame clock counter, the output of which is connected with the control input of the first switch, the second information input of which is connected to the first output of the second delay element, the input of which is connected to the first reset input of the address counter, is connected to the output of the address decoder, the second output of the second delay element is connected to the first reset input of the frame sync pulses, the second reset input of which is connected to the second reset input of the address counter is connected to the second input; the device is a zero trigger; the output of the second switch is connected to the control input of a gene A single pulse generator, the output of which is connected to the clock input of the address counter and the second input of the OR element, is the control output of the device. /five FROM From p R  L 22 k7 21 FIG. 2