SU1661776A1 - Device for interfacing microprocessor systems to external devices - Google Patents

Abstract

The invention relates to computing technology and is intended for use in microprocessor systems of information-measuring equipment and automation of technological processes based on the K1810BM86 microprocessor. The aim of the invention is to simplify the device for interfacing a microprocessor system with an external device. The principle of operation of the proposed device is based on the use of a bus driver as a pulse separator for two functional units operating on a common line. The device uses triggers, pulse shapers, the element OR NOT, bus driver, current-limiting resistors. 2 Il.

Description

The invention relates to computing and can be used in microprocessor-based systems of information-measuring equipment and automation of technological processes.

The purpose of the invention is to simplify the device.

FIG. 1 shows a diagram of the device; in fig. 2 - timing charts of the device.

The device contains input 1, trigger 2, generator 3, driver 4 and 5 pulses, element OR NOT 6, bus driver 7, trigger 8, bus 9 of zero potential, output 10, microprocessor 11, current-limiting resistor 12, bus 13 of a single potential, current limiting resistor 14.

The device works as follows.

In the initial state, the device at input 1 maintains a logical zero level coming from an external device, whereby the trigger 8 is set at its single input to the single state, and a logical zero is maintained at its inverse output. The clock pulses of the microprocessor generator 3 are fed to the synchronization input of trigger 2 and rewrite the input logic level zero to the output of trigger 2, the outputs of the formers 4 and 5 pulses, which are triggered by a positive front, maintain the logic zero levels, so the logical output the unit and the bus driver 7 transfers the logical unit from the input / output of the microprocessor 11 to the synchronous input of the trigger 8.

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When a logical unit i of an access request to the local channel of the microprocessor system (signal U1 in Fig. 2) arrives at the information input of trigger 2, it is copied to the direct output of trigger 2 (signal U2 in Fig. 2) by the following positive edge of generator 3 pulses, which necessary to synchronize the request to access the local channel with the operation of the microprocessor system. A positive edge at the forward output of flip-flop 2 triggers a shaper of 4 pulses. The pulse shaper 4 generates a short positive pulse with a duration approximately equal to the period of the clock pulses of the generator 3 (U4 in Fig. 2). The clock pulses in the timing diagram are represented by the signal U3. The pulse from the output of the pulse former 4 passes through the OR-NOT 6 element, is inverted and supplied (signal U6 in FIG. 2) to the control input of the bus driver 7, as a result of which the latter switches to the signal transmission mode from the information input to its bi-directional input /output. In this case, a logical zero from the information input of the bus driver 7 for the duration of the zero control signal is fed to the input / output of the bus driver 7 and then to the input / / output of the microprocessor 11. The bi-directional RQ / EO or RQ inputs are used as the input / output of the microprocessor 11 / ET, which are the access request entries that allow access to the trunk. The microprocessor 11 senses this negative impulse or request from an external device for access to the local channel and, after its termination, responds with a negative impulse to the same input / output (U 7) at the end of the current channel cycle or in the idle cycle, which is a message about Because the negative impulse on the UE equal to the input of the bus driver 7 has already ended, the driver 7 transmits the negative impulse of the microprocessor from the input / / output to its output and then to the trigger input trigger 8 (signal U 7). Trigger 8 positive (back)

the front of the pulse U is the left state,

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goes to zeroing by rewriting

0 5 Q

0

five

0

five

five

ches zero of its information entry to exit. At the same time, the inverse output of the trigger 8 is set to a high level of access resolution,. (signal U8), communicating with an external device via output terminal 10 to release the local channel, and the external device is connected to the channel.

After working with the channel, the external device removes the request signal, and a logical zero (U1) is set at the input terminal 1, this sets the trigger 8 to one and removes the access permission from the terminal 10. The first positive edge of the generator 3 pulses translates trigger 2 in the state of logical zero and at its inverse output, the level of the logical unit is formed, which starts the pulse shaper 5 forming a short pulse (U5 in Fig. 2). This impulse passes through the device in the same way as the impulse driver 4, which was described above, and enters the input / output of the microprocessor 11. The microprocessor 11 perceives it as a signal to terminate the channel capture and after two cycles takes control of the channel to itself .

Resistors 12 and 14 provide the operation of the device, forming the potentials of the logical unit at the input / output of the microprocessor 11 and you-. during the bus driver 7 while they are in a high-impedance state, eliminating the uncertainty of the signals at these terminals.

Claims (1)

Invention Formula A device for interfacing a microprocessor system with an external device containing an OR-NOT element, the first and second current-limiting resistors, characterized in that, for the sake of simplicity, two pulse shapers, a bus driver, and a first and second trigger are entered into it. the trigger is the information input of the device and is connected to the setup input of the second trigger; the forward and inverse outputs of the first trigger are connected respectively to the inputs of the first and second pulse drivers s, the outputs of which I connected respectively to the first and second inputs of an OR-NOT element, the output of which is connected to the control input of the bus driver, whose information input is connected to the zero potential bus of the device and to the information input of the second trigger, the information output of the bus driver, is connected to the synchronous input of the second trigger, and through the first current limiting resistor with the unit potential bus, the output of the second trigger is the output of the device, the information input / output of the bus driver is the information input / output of the device and through the second current-limiting resistor connected to the unit potential potential bus, the output of the first generator trigger FIG. /.