SU738134A1 - Pulse delay device - Google Patents

Description

(54) DEVICE FOR DELAYING PULSES

The invention relates to radio engineering and can be used in radiolocation, in particular, to form a delay of input pulses depending on their frequency Tatc, so that the delayed pulse precedes the subsequent periodic pulse by a constant cycle. . A device for delaying pulses is known, which contains a clock pulse generator two pulse counters, one of which is connected directly to the code comparison circuit and the other through a memory device, two coincident-controlled triggers, the output of each of which is connected to the corresponding pulse counter 1 A disadvantage of the known device is that it does not allow the delay value to vary depending on the frequency of the input pulses. It is also known a device for delaying pulses, comprising a clock pulse generator, two counters, a trigger. two elements And, the main delay shaper and the forming delay of the input pulses, depending on their frequency so that the delayed pulse precedes the subsequent periodic input pulse by a constant value 2. The disadvantages of this device for the delay of pulses are in the unbalanced formation (in each period incoming pulses) of several delayed pulses, which are ahead of the subsequent periodic input pulse at a different time interval, as well as in the complexity of the device, A large number of elements in the scheme. The purpose of the invention is to expand the functional capabilities and simplify the device. The goal is achieved in that a device for delaying pulses, containing a clock pulse generator, two counters, a trigger controlled by the first AND element, a main delay generator and a second AND element, are entered by h AND elements, a rewriter unit and an auxiliary delay delay generator, the output of which is connected with a zero input trigger and a fault input of the first counter, the output of the main driver - delay is connected to the input of the auxiliary delay driver and to the enable input of the rewriter, the inputs of which are the swarm is connected to the corresponding one-bit outputs of the first counter, and the outputs are connected to the corresponding one-bit setting inputs of the second counter, the inverse output of the last bit of the first counter is connected with the first element I, whose output is connected to the inputs of both meters, the inputs of each of the II elements And connected to the corresponding bitwise outputs of the second counter. The drawing shows a structural electrical circuit diagram of a device for delaying pulses. . The proposed device contains a generator of 1 clock pulses, counters 2 and 3. Counter 2 is connected via rewriting unit 4 with counter 3. Trigger 5 controls the first E7} I andB element, the output of which is connected to the counters 2 and 3. Inputs of the second element AND , 7 are connected to the corresponding one-by-one outputs of the counter 3, the output of the element AND 7 is the output 8 of the device. The device input 9 is connected to a single trigger input 5, a fault input of the counter 3 and an input of the main delay generator 10, the output of which is connected directly to the enable input of the rewrite unit 4, and through the auxiliary delay driver 11 with zero, the trigger input 5 and the reset input of the counter 2. Igtersny the output 12 of the last discharge of the counter 2 is connected to the input of element 6, and the output of the generator 1 is connected to another input. The inputs of the elements 13 and .. ,, 13 | connected to the corresponding one-bit outputs of the counter 3, the outputs of these elements are the outputs 14 ... 14 of the device. The device for the rear panel operation is as follows. After powering up, the device switches to the steady state after receiving 1–2 periods of input pulses. In the state preceding the arrival of the input pulse, the trigger 5 is in the control state, the element 6 is open, the clock pulses from the output of the generator 1 clock pulses arrive at the input of counters 2 and 3 through the element 6. When the input pulse arrives on the device input 9 is reset by the counter 3 and the trigger 5 is set to one state, the element 6 is closed, while the counter 2 records the number of clock pulses that fit in the time interval T, where T is the pulse period of the input pulses. At the end of the input pulse, the main shaper 10 of the delay (by applying a pulse to the enabling input of the rewriting unit 4) produces a permission to overwrite the number corresponding to the time T from counter 2 to counter 3 in the return code. At the end of the pulse from the output of the main delay driver 10 (i.e., rewriting), the auxiliary delay driver 11 sets the counter 2 and the trigger 5 to the zero state. At the same time, the And 6 element opens and the counters 2 and 3 start counting the clock pulses. T-C time, equal to the delay time of the output pulse relative to the input one, where T is a constant value, is equal to the delay time of the delayed output pulse relative to the subsequent input pulse (with the number of pulses in Counter 3 corresponding to of pulses, in the time interval ukladyvayuschihs C) for output of the AND element 7 and the outlet 8 of the device is a pulse after advancing .duyuschy input pulse on .S-. Similarly, at the outputs of elements 13 .... „. 13 j and at the outputs of the device 14 ... 14 Y also appear pulses leading the next input pulse at the corresponding constant time intervals C When the next input pulse arrives. The input 9 of the device repeats. Thus, from the output 8 of the device, the pulses are removed, delayed by the time T-tr, and a constant value determined by the frequency of the generator of clock pulses and the number decrypted by the element And b, and not dependent on the pulse frequency, C 14 .. ,, .., 14 j. the devices are also taken pulses, o.perezhdyayuschie subsequent input impulses, respectively, at constant intervals of time, ... 17 ,, independent of the following frequency of the input pulse. 573 In the absence of input pulses, the counter 2 counts the incoming clock pulses until its last bit is set to one and the signal from the inverted output 12 of the last bit of the meter closes AND 6. This stops the flow of clock pulses to the clock. 2 and 3, thereby preventing the output of false output pulses at the outputs 8, 14 ... 14 of the device. The described construction and application of the AND elements in the scheme of the proposed device expands the functional capabilities of the device for delaying pulses by forming a series of n delayed pulses leading the subsequent periodic pulse by various constant time intervals. In addition, the proposed device is more known. invention of the mule

A device for delaying pulses, 25 containing generator-clock pulses, two counters controlled by a trigger, the first element I, whose input is connected to the output of the pulse-clock generator, the main delay generator, whose input is connected to the input of the device, a single trigger input and a second reset input counter, the second element And, b which inputs are connected to

Sources of information taken into account in the examination

1. USSR author's certificate number 206892, cl. H 03 K 5/153, 19.05.66.

2. USSR author's certificate number 529554, cl. H 03 K 5/153, 15.04.75 (prototype). 4 corresponding output outputs of the second counter, characterized in that, in order to extend the functionality and simplification, AND elements are introduced into it, the rewrite unit has an auxiliary delay generator, whose input is connected to the zero TpOT-reipa with a zero and one source of the first counter, the output of the main the delay driver is connected to the input of the auxiliary driver for ajerzh and and with the permitting input of the block of the realsiste etod1 of which are connected to the so6t: ik, and the output is with the corresponding one-bit inputs of the second counter, the inverse of the last bit of the first counter of the first counter is connected to the code of the first AND element, the output of which is connected to the inputs of both counters, the inputs of each of the elements And connect with the corresponding ps) discharge outputs second counter.

Claims (1)

Claim . A device for delaying pulses, 25 comprising a clock generator, two counters, a trigger element I, whose input is connected to the output of a clock, the main delay driver, whose input is connected to the device input, a single trigger input and a reset input of the second counter, the second element And, the inputs of which are connected to the corresponding bit outputs of the second counter, characterized in that, in order to expand the functionality and simplify, And the And elements, the rewriting unit and the auxiliary delay driver, each of which is connected to the zero input of the trigger and the dump input of the first counter, the output of the main delay driver is connected to the input of the auxiliary delay driver and with the enable input of the block ’“ Гёёпапсси ^ до'дь! which is connected to the corresponding bit outputs of the first counter, and the output to the corresponding bit inputs of the second counter, the inverse output of the last bit of the first counter is connected to the input of the first element And, the output of which is connected to the inputs of both counters, the inputs of each of and the elements And are connected to the corresponding bit outputs of the second counter.