SU1640685A1 - Counter-type adder - Google Patents

Description

one

(21) 4637415/24

(22) 01/13/89

(46) 07.04.91 on Bul. N 13

(72) V.A.Mindalev and S.N0Subbotin

(53) 681.325 (088o8)

(56) USSR inventor's certificate 1043638, cl. G 06 F 7/50, 1982 „

Ugryumov EoNo Designing of elements and units of EVMo - M0: Higher School 1987, s0195, 196, fig. 11, 14,

(54) ACCUMULATING SUMMATOR

(57) The invention relates to computing and can be used in information transmission devices. The aim of the invention is to improve the accuracy of the accumulating adder when used as an averaging device of the input number for phase-adjustment circuits. The accumulating adder contains register 1, combinational adder 2, two majority elements 3.4, element 5, element 6, trigger 6, element EXCLUDE- DIEE OR 8, the synchronization bus 9 and the input number bus 11D, functionally interconnected 1 sludge

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The invention relates to computing and can be used in devices for transmitting information about

The purpose of the invention is to improve the accuracy of the accumulating adder when used as an averaging device of the input number for phase-adjustment circuits 0.Q

The drawing shows a functional diagram of the accumulating adder.

Accumulator adder contains register 1, combinational adder 2, first 3 and second 4 majoritarian elements, elements NOT 5 and AND 6, trigger 7, element EXCLUSIVE OR 8, synchronization bus 9 and input number 10, interconnected functionally 2

The accumulating adder as an averaging device of the input number works as follows

The code of the first term is stored in 25 register 1, and the code of the second term is received via bus 100

In the combinational adder 2, two numbers are added, the first of which is supplied via bus 10, and the second is generated from register 1 outputs. The sum generated by the synchronization pulse received via synchronization bus 9 is written to register 1. The element EXCLUSIVE OR 8 compares the characters of the input and output numbers "If the values of the sign bits at the output of the accumulating adder and the input number are the same (accumulation of positive or negative numbers occurs), then the output level of the EXCLUSIVE OR 8 logical level l is supplied to the data input Trigger 7 and is recorded in it on a pulse sinhronizatsiio45

This level of logical zero is multiplied by AND 6 for the duration of the synchronization pulse and goes to the first inputs of the majority elements 3 and 4, to the second inputs of which the level of logical zero arrives, and, regardless of the level at the third inputs, at the outputs of the majority elements 3 and 4 there is a level of logic zero, which is.,. steps onto the setup inputs of register 1, without affecting them; the accumulating adder in this case sums the input numbers and the result accumulates in

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register I, replacing the previous content0

If the input number sign has changed and the sign bits at the output of the accumulating adder and input number are different (O and 1 or 1 and O, respectively), this means that the accumulation needs to be stopped, because the clock frequency at the reception of the phase adjustment circuit in this case it is necessary to reset or set to one state depending on the sign of the input number

With different signs of input and output numbers of the accumulating adder at the output of the EXCLUSIVE OR 8 element, the level of the logical unit is generated, which arrives at the information input of the trigger 70 But the synchronization pulse, the level of the logical unit is written to the trigger .7 and from its output goes to the first input of the And 6 element, the output of which is formed by a pulse of duration equal to the synchronization frequency pulse. This pulse arrives at the first inputs of the majority elements 3 and 4 "If the input of the accumulating adder is positive A number, then the third input of the majority element 3 receives the level of the logical unit, and the third input of the majority element 4 - the level of the logical zero 0 The output of the majority element 3 forms the level of the logical unit, which enters the input of the register 1 at zero, and at the output of the majority element 4 - the level of logical zero 0

Logic zero levels are formed at the bit outputs of register 1. If a negative number is at the input of the accumulating adder, then the third input of the majority element 3 receives the logic zero level, and the third input of the majority element 4 forms the logic level. zero, and at the output of the majority element 4 - the level of the logical unit, which enters the input of the register 1 in the unit. On the bit outputs of the register 1, the levels of the logical unit are formed Register 1 is zeroed or set to one

and again begins to accumulate input numbers

Setting the register 1 accumulator to zero or a single state is necessary to correct the characters of the input and output numbers

The efficiency of using the proposed accumulator adder in the phase adjustment circuit is to improve the accuracy of the phase adjustment of the clock frequency. The scheme determines the equality of the clock frequencies on the transmission and reception, which allows to increase the noise immunity of the system

Invention Form

The accumulating adder containing the combinational adder and the register discharge outputs of which are connected respectively to the inputs of the first group of the combinational adder, the inputs of the second group of which are connected to the input number bus of the accumulating adder, the discharge outputs of the combinational adder are connected respectively to the information inputs of the second majority element of the accumulator, synchronization input which is output connected to input

connected to the synchronization bus of the nakap-installation in a single state of the relativizing adder, distinguished by Ayu-Gistr0

y and so that, in order to improve accuracy when using the accumulating adder as a device for averaging the input number for phase-adjustment circuits, the first and second major elements, the element NOT, the element AND, the trigger and the element EXCLUSIVE OR, and the output the sign bit of the register is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the sign bus discharge of the input number and to the input of the element NO, the output of the EXCLUSIVE OR element is connected to, the trigger information input, the output of which is connected to the first input of the element I, the second input of which is connected to the synchronous inputs of the trigger and the register, the output of the element I is connected to the first inputs of the first and second major elements, the second inputs of which are connected to the zero potential bus, the output of the element is NOT connected to the third input of the first the major element, the output of which is connected to the input of the installation in the zero state of the register, the input of the element is NOT connected to the third

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Claims (1)

Claim An accumulating adder containing a combinational adder and a register, the discharge outputs of which are connected respectively to the inputs of the first group of the combinational adder, the inputs of the second group 25 of which are connected to the input number bus of the accumulating adder, the discharge outputs of the combinational adder are connected respectively to the information inputs of the register, synchronization input which is connected to the synchronization bus of the accumulating accumulator, the difference is that, in order to increase accuracy when using accumulators In addition, the first and second majority elements, the element NOT, the AND element, the trigger, and the EXCLUSIVE OR element are inserted into it as an averaging device for the input number for phase adjustment circuits, and the output of the register bit is connected to the first input of the EXCLUSIVE OR element, the second input of which connected to the sign bit of the input number bus and to the input of the element NOT, the output of the element EXCLUSIVE OR connected to the information input of the trigger, the output of which is connected to the first input of the element AND, the second input of which it is one with the trigger inputs of the trigger and register, the output of the And element is connected to the first inputs of the first and second majority elements, the second inputs of which are connected to the zero potential bus, the output of the element is NOT connected to the third input of the first majority element, the output of which is connected to the input to the zero state of the register , the input of the element is NOT connected to the third input of the second majority element, the output of which is connected to the input of the unit into a single state of the register ”