RU2546569C2 - Summation device - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in automatic control systems, self-compensators in which there is need to obtain a summing result via algebraic addition of a large number of binary numbers. The technical result is achieved using a summation device which includes an adder accumulator, an AND element, as well as a parallel register, which is the random access memory of the adder, n first least significant inputs of the adder accumulator, (m+1) first most significant inputs of the adder accumulator, the sign input of the device, the clock input of the parallel register, the carry output of the adder accumulator, the first input of the AND element and the device operating mode selecting input.

EFFECT: faster operation and higher reliability of the summation device.

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Description

The invention relates to computer technology and can be used in automatic control systems, auto-compensators, in which it is required to obtain the result of accumulation using algebraic addition of a large number of binary numbers.

A device for summing binary numbers is known (patent SU 1022153, publ. 06/07/1983), which contains an accumulating adder, counter, two elements FORBID, the first and second elements I.

The disadvantage of this device is that it cannot work in additional code and has a large amount of equipment.

The closest analogue (prototype) of the claimed device is a device for adding binary numbers (patent SU 1103223, publ. 07.15.1984). This device for adding binary numbers contains not only an accumulative adder, counter, two elements FORBID, the first and second elements OR, but also with the aim of expanding functionality by providing the ability to add binary numbers represented by both additional and reverse codes, contains the first , second, third, fourth, fifth and sixth elements AND and elements NOT, which is a feature of the device.

A disadvantage of the known device is the low speed due to the large amount of equipment.

The task to which the invention is directed is to simplify the device, increase the speed and reliability of the device.

This problem is solved due to the fact that the device for summing contains an accumulating adder, element 2I, as well as a parallel register, which is the RAM of the accumulating adder. In this case, the n first junior inputs of the accumulating adder are connected to the inputs of the device, and (m + 1) the first senior inputs of the accumulating adder are connected to the sign input of the device, the inputs of the accumulating adder are connected to the inputs of the parallel register, the outputs of which are connected to the second inputs of the accumulating adder and to the outputs devices, the synchronization input of the parallel register is connected to the synchronization input of the device, the transfer output of the accumulating adder is connected to the first input of element 2I, the second input of which о is connected to the input of the device mode selection, and the output is connected to the transfer input of the accumulating adder.

A distinctive feature of the prototype is that the proposed device uses a parallel register, which allows you to sequentially sum the input numbers with each clock signal, excluding the counter, the first and second elements OR, the second, third, fourth, fifth, and sixth elements contained in the above prototype And, the element is NOT, the first and second elements of the prohibition.

Figure 1 presents a block diagram of a device for summing.

The device for adding contains:

1 - accumulating adder;

2 - parallel register;

3 - element 2I;

4 - synchronization input;

5 - mode selection input.

The essence of the present invention lies in the fact that the first information inputs of the accumulating adder 1 receive a number x, expressed by a reverse or additional code, represented by n-information and one sign digit, and the first sign input is connected to the (m + 1) senior first the inputs of the accumulating adder 1, and the result obtained is represented by (n + m) -information and one significant digit in the reverse or additional code. The obtained result is recorded in parallel register 2 by the clock signal supplied to the synchronization input 4. From the output of parallel register 2, the obtained result y goes to the output of the device and to the second information inputs of the accumulating adder 1.

The device allows you to sum arrays of numbers by algebraic addition of the next (n + 1) -digit, including sign digit, of the (k + 1) -th input number with the result of adding the previous k numbers stored in register 2 after the k-th clock signal input sync 4.

When summing the numbers expressed by the reverse code, a single signal is supplied to the input of the mode 5 selection of element 2 AND 3 and the cyclic transfer circuit closes. In this case, the single and zero transfer signals from the transfer output of the accumulating adder 1 are fed through element 2I 3 to the transfer input of the accumulating adder 1.

When summing the numbers expressed by an additional code, a zero signal is input to the mode 5 input of element 2I 3 and the cyclic transfer circuit of the accumulating adder 1 receives a zero signal from the output of element 2I 3.

A device containing m + n information bits, when summing the numbers of the same sign and the maximum modulo, allows the addition of 2 ^m numbers of bit capacity (n + 1), including the sign bit.

Thus, due to the introduction of a parallel register and new connections, the positive effect of the proposed device is to reduce the amount of equipment and, therefore, to increase the speed and reliability of the device.

Claims (1)

A summing device comprising an accumulating adder, element 2I, as well as a parallel register, which is the RAM of the accumulating adder, characterized in that the n first lower inputs of the accumulating adder are connected to the inputs of the device, and (m + 1) the first senior inputs of the accumulating adder are connected with a significant input of the device, the outputs of the accumulating adder are connected to the inputs of the parallel register, the outputs of which are connected to the second inputs of the accumulating adder and the outputs of the device, The synchronization progress of the parallel register is connected to the synchronization input of the device, the transfer output of the accumulating adder is connected to the first input of element 2I, the second input of which is connected to the input of the device mode selection, and the output is connected to the transfer input of the accumulating adder.