SU1637024A1 - Converter - Google Patents

Abstract

The invention relates to computing and can be used, for example, to connect computers with control objects, simulate radar signals, build controlled delay lines. The purpose of the invention is to expand the functionality. The converter contains a reference and vernier pulse generators, two AND elements, an OR element, two delay elements, a single vibrator and N conversion channels, each of which contains reference and vertex pulse counters, six AND elements, five OR elements, a D-trigger, four triggers , start bus, high and low bits of the input code, two Start tires, two Stop buses, a Code-interval and Interval-code tires, two output code tires, an output interval bus, a reset bus and a logical unit bus. The goal is reached by providing a forward and reverse multichannel vernier conversion. Moreover, in the multichannel code-to-interval mode, the vernier interpolation is used, and in the interval-to-code mode, the accuracy of the conversion is increased by using the total frequency of the reference and vernier generators to fill the counters. In both modes, regardless of the number of channels, only two oscillators are used. 1 il. S (L o w. J i

Description

The invention relates to computing and can be used, for example, to connect computers with objects of control, simulate radar signals, build controlled line delay.

The purpose of the invention is to enhance the functionality by providing a direct and inverse multi-channel conversion.

The drawing shows a flowchart of a nonius code converter in a time interval.

The converter contains reference and vernier generators 1 and 2 pulses, elements AND 3 and 4, element OR 5, elements 6 and 7 of the delay, one-oscillator 8 and N conversion channels, each of which contains a reference counter 9 pulses, vernier counter 10 pulses, elements AND 11-i

16, elements OR 17-21, D-flip-flop 22 triggers 23-26, start bus 27, tires 28 and 29 high and low bits of the input code, first bus 30 Start, first bus 31 Stop, second bus 32 Start, second bus 33 Stop, bus 3 Code-interval, bus 35 Interval-code, first and second tires 36 and 37 output code, bus 38 output interval, reset bus 39 and bus 0 logical unit cus

The Converter operates as follows.

An appropriate conversion mode is established in each channel in advance. When a signal is applied to the 3k bus, the code interval in this channel converts the code to a vertex interpolation interval. When a signal is sent to the bus 35 Interval Code on this channel, the interval is converted to a code on two subchannels.

Let us consider the operation of any channel in the mode of converting code to an interval. The signal on the reset bus 39 of the corresponding channel resets the counters 9 and 10 and the flip-flops 22-25. The operation of each channel is carried out independently of each other by applying the corresponding mode signals to the buses 3 and 35o. Then, over the recording bus 27 of the corresponding channel, the inverse code of the most significant bits is written to the counter 9 from the bus 28 and the direct code of the lower bits to the counter 10 from bus 29. To start the conversion, a signal is sent to the first bus 30 Start. At that, the trigger 23 is set to one state and the I 13 and C elements are opened. From the trigger 26, the enable signal is received on the And 11 and 12 elements, since the Code-interval conversion mode is set by setting the bus trigger to the single state -interval 3. Generators 1 and 2 operate continuously. The detection of the complete coincidence of their phases is carried out using the elements AND 3 and k, the delay element 6 and the one-channel 8o. Incomplete coincidences of the phases of the generators 1 and 2 have a shorter duration than the full ones, therefore with the help of the delay element 6 and the element AND b are blocked and

only complete phase matches are recorded. For this, the signal from the output of the element And 3 is fed to the first input of the element And k directly and to its input through the element 6 delay. The magnitude of the delay in delay line 6 is chosen to be less than the duration of a full phase match and a longer duration of the phase that precedes a full match. Such a choice of the delay value in the delay element 6 is possible because the duration of incomplete coincidence of the phases of the generators 1 and 2 until discrete coincidence increases discretely with discreteness determined by the choice of frequencies of the vernier and reference oscillators 1 and 2. With the specified choice of delay time, the And 4 element will only work when the phases of generators 1 and 2 coincide completely. For any duration of the signal at the output of the element And k, the single vibrator 8 generates a signal of constant duration, which ends when the pulses end 1 and 2, in which there is complete coincidence of their necessary in order to exclude from the vernier count and reference counters 9 and 10 residues pulse generators with incomplete coincidence of phases 1 and 2.

The pulses of complete coincidence of the phases of the generators 1 and 2 from the single vibrator 8 are transmitted through the open elements AND 13 to the inverse C inputs of the D-flip-flops 22. After the signal from the single vibrator 8 is terminated, the D flip-flops of the 22 channels to which signals from the first bus When the D-flip-flop 22 is set to one, the corresponding channel begins to perform a Vernier code conversion in a time interval. At that, the element 12 opens and the element 11 prepares for opening. The pulses of the vernier generator 2 pass through the open element 12 and begin to accumulate on the vernier counter 10, when overflowed, the trigger 2k is set to one state and the beginning of the output interval of the corresponding channel is formed on the output interval bus 38. At the same time, the element 11 is opened and the pulses of the reference generator 1 begin to accumulate on the reference counter 9, when overflowed, they are set to trigger condition triggers 22-25 | and the end of the output interval of the corresponding channel on the bus 38o is formed. The conversion cycle in the corresponding channel ends with 0. The result of the conversion over the i-th channel is determined by the formula -c (

t ,; To NoiH-hT; (N4waKcrNHl) (

where T0 is the period of the reference generator; N. - the number of pulses recorded by the reference counter 9 of the 1st channel until its overflow; h - the base of the number system

in the i-th channel;

0 (; is the number of low-order bits of the input of the “- code, allocated for vernier interpolation in the i-th channel;

K .... - the maximum number of pulses recorded by a vernier counter 10 of channel 1; the number of pulses recorded by the vernier counter 10 of the 1st channel until it overflows

H MO KS /

NHi

coincidence of generators 1 and 2. For any coincidence of pulses from generators 1 and 2 on the element OR 5, they turn into one extended pulse and therefore, in order to form two pulses, on the delay element 7 any coincidence pulse is delayed and added to the element OR 5 The total delay time on delay elements 6 and 7 is chosen to be longer than the pulse duration from the oscillators 1 and 2, but shorter than the periods of the oscillators 1 and 2.

Thus, the total frequency of the pulses from the generators 1 and 2 is always formed on the element OR 5. The pulses from the element OR 5 through the open element AND 16 arrive at the elements

Both 14 and 15. In each channel in this mode, the interval is converted into code by two subchannels. To start the first subchannel after resetting counter 9, a signal is given

5 start-up on the first bus. Start 30 "With this, trigger 23 is set to one and the AND 1A element is opened. The pulses from the output element And 16 through the element OR 20 post

Thus, in the mode, 30 are converted to a summing input of a code counter into a conversion interval of 9. Upon completion of the converted intel, it allows you to convert the code into the time interval using Nn channel irrespectively of the number of channels. two oscillators - reference 1 and vernier 2, which have a higher frequency stability than the running generators.

In the converter in any channel, it is possible to set the mode of interval conversion to code. For this, a signal is sent to the bus 35 in the corresponding channel on the interval-code, which sets the trigger 26 to the zero state. At the same time, elements 11 and 12 are closed and element 1b opens. In this mode, using35

the terrestrial signal is sent to the first bus Stop 31 through the element OR 18, the trigger 23 is set to the zero state, the AND element is closed and the code corresponding to the input interval of the first subchannel is formed on the counter 9. The code from counter 9 is fed to the first bus 36 of the output-40 code. To start the second subchannel after resetting the counter 10 in O, a signal is sent to the second bus Start 32. The trigger 25 is set to one, the element 15 opens and the pulses from the element 16 arrive through the element 15 and the element OR 21 into the summing the input of the counter 10. At the end of the converted interval, a signal is fed to the second bus

45

In addition, delay element 7 is 50 and 33 Stop, through element OR.19 and element OR 5. Element OR 5 is set to the zero state, it drives the frequencies of the pulses from the generators, trigger 25, closes element 15 1 and 2. In order on the element OR 5 was formed full of cha55

from the generators 1 and 2, the total pulse sequence at the output of the element OR 5 adds pulses from the delay element 7, which forms delayed pulses

and on the counter 10, a code is generated corresponding to the input interval of the second subchannel. The code from counter 10 is fed to the second bus 37 of the output code.

In the interval conversion mode, the code counters of each subchannel in

five

The terval sends a signal to the first bus Stop 31 through the OR element 18, the trigger 23 is set to the zero state, the AND element is closed, and a counter corresponding to the input interval of the first subchannel is generated on the counter 9. The code from counter 9 is fed to the first bus 36 of the output-0 code. To start the second subchannel after resetting the counter 10 on O, a signal is sent to the second bus Start 32. The trigger 25 is set to the one state, the AND 15 element opens and the pulses from the AND 16 element go through the AND 15 element and the OR 21 element to the summing input of the counter 10 At the end of the conversion interval, a signal is applied to the second screen.

well, 33 Stop, through the element OR.19 the trigger 25 is set to the zero state, the element is closed AND 15

and on the counter 10, a code is generated corresponding to the input interval of the second subchannel. The code from counter 10 is fed to the second bus 37 of the output code.

In the interval conversion mode, the code counters of each subchannel in

The channel is filled with a clock frequency of twice the frequency from one generator, which makes it possible to halve the conversion error due to unsynchronization with the cycles of the beginning and end of the interval being converted.

delays, the second element OR and N channels of transformation, are identical to the first one, each of which is entered into the first and second bus Stop, second bus Start, tires Code-interval Interval-code, third and fourth triggers, fifth, sixth, seventh eighth elements And third quarter

Claims (1)

Claims of the invention, fifth and sixth elements OR A vernier code-to-time converter containing a reference and vernary pulse generators, the outputs of which are respectively connected to the first and second inputs of the first And element, the output of which is connected to the first input of the second And element and to the input of the first delay element, the output of the first delay element through the second delay element is connected to the first input of the second OR element, the second input of which is combined with the first inputs of the third AND elements of each conversion channel, the third input is combined with the first inputs of the fourth AND elements of each conversion channel, and the output which is connected to the second inlet 20 is connected to the first inputs of the eighth second element AND, the output of which elements AND of each conversion channel, the second input of the eighth element AND in each channel It is connected to the inverse output 25 of the fourth trigger, the S and R inputs of which are the Code-Interval and Interval-Code buses, respectively, and the direct output is connected to the third input of the fourth And element, the output of the co-information input of the reference counter 30 is connected with the first input of n - pulses and a direct information OR element, the second input of which is connected to the one-vibration input, and the first conversion channel performed on the first and second hera, the first OR element, the third and fourth And, D-flip-flop elements, support and non Pulse counters, whose recording inputs are combined and are a recording bus, are inverse the input of the vernier pulse counter are the high and low bits of the input code, respectively, and the overflow outputs of the reference and vertex pulse counters are connected respectively to the first input of the first OR element and the S input of the second trigger, the output of which is the output interval bus, and R- the input is combined with the R-input of the D-flip-flop and is connected to the output of the first OR element, the second input of which is the reset bus, the first inputs of the third and fourth AND elements are respectively connected to the outputs of the reference and They are pulse generators, and the second inputs are combined and connected to the output of a D-flip-flop, D-v of which is a bus of a logical unit, the third input of the third element I is connected to the output of the second flip-flop, and the S-input of the first trigger is the first bus characterized in that, in order to expand the functional possibilities by providing a direct and inverse multi-channel conversion, a second element is introduced into it . 55 It is connected to the output of the sixth element And, and the output is connected to the summing input of the reference counter; Pulse 35 whose reset input is combined with the reset terminal of the Vernier pulse counter and is the reset bus, and the information output is the first bus of the output code, the information output of the Vernier pulse counter is the second bus of the output code, and the summing input is connected to the output of the sixth OR element, whose inputs are respectively connected to the outputs of the fourth and seventh And elements, the first input of the last of which is combined with the first input of the sixth And element and connected to the output of the eighth And element, and the second input is connected to the third trigger output, the S input of which is the second Start bus, and the R input is connected to the output of the fourth OR element, the first input of which is the second bus Stop, and the second, the input is combined with the R input of the P-flip-flop and the first input of the third OR element, the second input of which is the first bus Stop and the output 45 .50 delays, the second element OR and Nf conversion channels, identical to the first one, each of which contains the first and second Stop buses, the second Start bus, the Code-interval and Interval-code buses, the third and fourth triggers, the fifth, sixth, seventh and eighth AND elements and the third, fourth, fifth and sixth elements OR the output of the first delay element through the second delay element is connected to the first input of the second OR element, the second input of which is combined with the first inputs of the third AND elements of each conversion channel, the third input is combined with the first inputs of the fourth AND elements of each conversion channel, and the output is connected with the first inputs of the eighth elements AND of each conversion channel, the second input of the eighth element AND in each conversion channel is connected to the inverse output of the fourth trigger, the S and R inputs of which Are the Code-Interval and Interval-Code buses, respectively, and the direct output is connected to the third input of the fourth AND element, the output of which is connected to the first input of the n - that OR element, the second input of which five It is connected to the output of the sixth element And, and the output is connected to the summing input of the reference counter; Pulse 35 whose reset input is combined with the reset terminal of the Vernier pulse counter and is the reset bus, and the information output is the first bus of the output code, the information output of the Vernier pulse counter is the second bus of the output code, and the summing input is connected to the output of the sixth OR element, whose inputs are respectively connected to the outputs of the fourth and seventh And elements, the first input of the last of which is combined with the first input of the sixth And element and connected to the output of the eighth And element, and the second input is connected to the third trigger output, the S input of which is the second Start bus, and the R input is connected to the output of the fourth OR element, the first input of which is the second bus Stop, and the second, the input is combined with the R input of the P-flip-flop and the first input of the third OR element, the second input of which is the first bus Stop and the output 5 0 It is connected with the R input of the first trigger, the output of which is connected to the second input of the sixth And element and to the first input of the fifth And element, the output of which is connected to the C input of the D-trigger, and the second input is combined with the second inputs of the fifth And elements every 163702410 The first conversion channel and connected to the one-shot output, the outputs of the second flip-flops of each of the N-1 conversion channels are the corresponding buses in the output interval.