SU1626253A1 - Square rooter - Google Patents

Abstract

The invention relates to computing and can be used to calculate the square root in the functional transformations of the information. The purpose of the invention is to increase the speed and accuracy of the square root calculation. The goal is achieved by introducing the ROM group and the read control block with the appropriate connections. This allows you to make the number from which the number root is extracted, the immediate address of the ROM in which the result is programmed, which leads to an increase in speed and savings in equipment. 2 Il.

Description

The invention relates to computing technology, namely to special computing devices for functional information conversion.

The purpose of the invention is to increase the speed and reliability of calculations.

Fig, 1 shows a block diagram of the device; Fig. 2 shows the format of the number from which root calculations and zones are distributed in this format for addresses of each memory block.

The device contains registers 1 and 2, delay element 3, read control block 4, memory blocks (ROM) 5-10 groups, block 4 contains OR elements 11-14. decoder 15.

The essence of the invention is based on the use of the following pattern:

12 1

22- (1 + 1) 2 12 + 2x1 + 1 4

З2 - (2 + 1) 2 22 + 2 x 2 + 1 9

42- (3+ 1) 2 32 + 2x3 + 1 t 16

52 (4 + 1) 2 42 + 2 x 4 + 1 25, etc.

In general, (n + 1) -th member of this sequence can be represented as (n + 1 n2 + 2n + 1, if we assume that the result of extracting the square root of an integer is an integer, then VА B and then A B2.

If we follow the increase in the number A, then from a certain value of B + 1, while 6-2B + 1. Thus, if we specify an error of 1, then for all numbers from A to A + 2B, the square root value will be B. H0VA- f2B + 1 -B + 1.

An increase in the number A by up to (2B + 1) does not cause a change in the square root value. Considering the above, you can write the following sequence:

... 5/25

6- / 25 + 2 x 5 +1 / 36 7 - 36T2 x 6 +1 V49

Yo

ABOUT

Yu

Os

go ate with

49+ 2x7 + 1

33 + 2 x 32 + 1 V1089 etc.

In the last example, if you specify an error of 1, the square root value 32 will be for all numbers from 1024 to 1088, i.e. 65 values.

Any integer A 1 in the binary number system can be represented as.

A a; X2 + am X 2m + amH

 + ... + aiX21 + aoX2 °, where ai 1, a (i-i) ... a0 0,1. This number is between 21 A 2 | +1. The square root of this number will be B - bi / 2 X 2 | / 2 + bi / 2 -1 X ... + bi X

X21 + bo X2 °, 1, bi / 2-i ... bo 0.1 if I is even,

where bi / 2 and

i + i

B b (i + ii / 2 X2 where L (| + jj / 2 ... bo

2 + ... + biX21 + boX2 °, 0.1, if I is odd.

If we go up the number A, the next value of the root will correspond to B + 1, while the number A will increase by 2B + 1. Multiplying by two numbers in the binary system corresponds to shifting the numbers to the left by one bit. Therefore, if the number is the highest bit yes the number B was 1/2, then the number of the highest bit of the number 2B

will be (+ 1). Thus, if VA

and go up the number A, the value of the root B + 1 will be in the case

O |

if it changes (-n- + 1} th digit of the number A,

however, the error may be 1. Changes in the bits below the specified one do not cause a change in the square root value. Therefore, when extracting the square root of a 1-bit number, you can not take into account the lower bits from 0th to 1 / 2th. Meaningful bits will be

from (-j- + 1) -th to the 1st. To reduce the error by half, it is necessary to halve the part of the number that is not taken into account, i.e. shifted by one bit to the right, the boundary of the significant number when extracting the square root. If you extract the square root of a .1-bit binary number with an error of 0.5, you can ignore

lower-order bits from 0th to (-y are 1} -th, and only changes in bits, starting from l / 2th to 1th, cause changes as a result of the square root.

FIG. Figure 1 shows a block diagram of a device for extracting the square root of all numbers limited to 20 bits. A memory chip with a 2K x 8 memory organization is used as a memory block (ROM). The memory block has 11

0 lines of the address from the 0th to the 10th bit, N 10 and 8 data lines, M 8, there is also an input Read permission. In the absence of a signal at this input, all 8 data lines of the memory unit are in the third state 5 of the high impedance state.

Memory block 5 is programmed for all numbers from 0 to 2047. The square root value from 2047 corresponds to 45. If you go upwards, the next feed value will be 46, and the root expression will increase compared to the previous 45 x 2 + 1 91, which corresponds to the binary system 1011011 (six bits, counting from zero 5). Thus, the next memory block is programmed not from the 6th digit of the input number / but from the 5th digit and further until the address part of the ROM is completely filled, i.e. on the 15th bit. Programming from the 5th row, not from the 6th, allows to obtain an error of the result not more than 0.5. ROM 6 covers all numbers from 2048 to 65535. The square root value from 65535 corresponds to 256 28. Next root value

5 257, while the root value will increase by 256 x 2 + 1 513, i.e. the change will occur in the 9th category de. Therefore, to get an error of no more than 0.5, the next ROM 7 must be programmed not from the 9th bit, but from the 8th bit of the input number, and further until the ROM address is completely filled, i.e. on the 18th digit of the number from 65536 to 324287.

The square root of 324287 is

5,724. The next value of 725 will be if the root value increases by 724 x x 2 + 1 1449, i.e. the change must occur in the 10th bit, and for an error of no more than 0.5, the following ROM 9 is programmed from the 9th bit of the input number and further to the 19th bit.

The selected ROMs have 8 data lines. Since in the example the input number can have all 20 bits significant, i.e. logical 1, then at some value the result of the square root can exceed 8 bits. For this, two more ROMs are inserted into the device, ROM 8 is connected in the address part similarly to ROM 7, and two data lines are intended to extend the size of the root extraction result (8th and 9th bits). ROM 10 operates in conjunction with ROM 9, and two data lines are also used to increase the result size.

The device works as follows.

The binary code of the number from which it is necessary to extract the square root is fed to the information inputs of register 1. By the Start signal, which goes to the control input of register 1, this code is written to the register and fed to the address part of ROM 5 ... ROM 10 and reading control block 4. Moreover, bits from 0th to 10th go to ROM 5, bits from 5th to 15th go to ROM 6, bits 8th to 18th go to ROM 7 and 8, and bits from 9th to 19th - on ROM 9 and 10.

Block 4 of reading control contains input elements OR 11 and 12, decoder 15 and output elements OR 14 and 13. Discharges from the 11th to 15th from the output of register 1 through the input element OR 11 of read control block 4 are sent to the first decoder skoda 15. The bits from the 16th to the 18th through the input element OR 12 of the read control block 4 are sent to the second input of the decoder 15, and the 19th bit to the third input of the decoder 15. If there are no logical units in the binary code of the number bit from the 11th to the 19th (Fig. 2), then the inputs of the decoder 15 will be an LLC code (0) and at the output of 1 de fratora signal 15 is generated for the read resolution of the ROM 5 which activates the outputs of the ROM 5. The outputs of the remaining ROM, ROM 6 ... 10 are in the high impedance state. The value of the square root stitched in this ROM 5 at the given address (number code) from the outputs of ROM 5 is fed to the information inputs of register 2. The trigger signal delayed by delay element 3 for the sampling time of the ROM is fed to the control input of register 2 and the binary code the square root value is written to register 2.

If in binary code numbers in bits 11 through 15 there are at least one logical 1, then this logical 1 through the input element OR 11 of the reading control block enters the first input of the decoder 15 and, in the absence of logical units in the bits From 16th to 19th, code 001 is generated at the inputs of the decoder.

At output 2 of the decoder 15, a readout signal is generated for the ROM 6. This activates the outputs of this ROM 6. The outputs of the remaining ROM 5, ROM 7 ... ROM 10 are in a high state.

impedance. The value of the square root stitched in ROM 6, by the address code from its outputs, also goes to the information inputs of register 2. If in binary code

the numbers in the bits from the 16th to the 18th there are at least one logical 1. and in the 19th section is logical O, then this (these) logical 1 through the input element OR 12 of the read control block enters the second

0 input of the decoder 15 and the code 010 is formed at the inputs of the decoder, if there was no logical 1 in bits 11 through 15, or 011 if there were at least one logical one in bits 11 through 15. this either

5 at the output 3 of the decoder 15, or at its output 4, the read resolution signals are generated, which are combined via the output element OR 13 and the output of this element is the read resolution signal

0 activates the outputs of the ROM 7 and ROM 8. The use of two ROMs in this case is due to the fact that the size of the square root of a 19-bit number may exceed the number of data lines

5 single ROMs (in this case, the number of data lines of one ROM is 8). Therefore, ROM 8 is used to increase data up to 10 bits; from the 0th to the 7th outputs from ROM 7, and the 8th and 9th bits - outputs

0 ROM 8.

If in the 19th digit of the code of the logical 1 number, then the code is set at the input of the decoder 15 of the read control block 4

100 if in bits from the 11th to the 18th there are no 5 logical 1. At the same time, output 5

The decoder 15 generates a read resolution signal. If in the 19th bit of the code the numbers are logical 1 and in the bits from the 11th to the 18th, there can also be logical 1, 0, then there can be a code at the inputs of the decoder

101, signal Read permission is produced at the 6th output of the decoder 15, code 110 at the 7th output and code 111 at the 8th output of the decoder 15. These outputs

5 5-8 decoder 15 are combined by the output element OR 14 of the read control block 4 and the output of the element OR 14 signal Read resolution activates the outputs of ROM 9 and 10. The remaining ROM 5 ... ROM 8 is in high impedance state. ROM 10, in this case, is used similarly to ROM 8 in the previous case to extend the size of the square root value to 10. Outputs from ROM 9 are bits 5 from 0th to 7th; 8th and 9th bits are from ROM 10. To determine the maximum size of the radicand and the amount of ROM in the device for extracting the square root, you must specify the number of address lines selected

ROM. In general, if the high-order address has the number N (0.1, ... N), then such a ROM can be programmed for all 2 addresses, i.e. for all numbers from 0 to 2, program the values of their square roots.

If the number of numbers from which the square root is to be extracted exceeds the size of the address part of the ROM, the next, second, ROM is programmed, starting with N / 2 bit of the number and further along (N / 2 + N) bit, t. e. the higher-order number of the second ROM will be the B / 2-digit number from which the square root is extracted.

The next, third ROM will be programmed, starting with (3N / 2): 2 3N / 4 bits of the number and the most significant bit of the address will correspond to 3N / 4 + N 7N / 4 bits of the input number.

The next, fourth ROM is programmed, starting with 7N / 4-.2 7N / 8 bits of the number, and the most significant bit of the address corresponds to 7N / 8 + N - 15N / 8 bits of the number, etc.

Thus, the number of the higher bit of the first ROM is N, the second is 3N / 2, the third is 7N / 4. fourth isn / 8th In the general form, the numbers of the higher bits of the ROM will be described by the expression Nx2k-1/2 - Nx (2-1 / 2k 1), where k is 1, 2, 3 .... is the number of ROM. The limit of this expression at k - ° o characterizes the maximum width of the radicand, i.e.

Hm N (2-,) 2N. (1)

k - oo

Therefore, using the ROM, you can program the square root function for all numbers whose binary code is twice the size of the address part of the ROM.

To determine the number of ROMs, to implement expression (1), it is necessary to solve the equation

N (2-1 / 2k-1) 2N-1;

2N-N2 / 2IM -2N-1;

N / 2k 1-1;

2k 1 - N;

k-1 loga N;

k - 1 + loga N (2)

Since the number of ROMs can only be an integer, when calculating k from expression (2), the result should be rounded up to an integer, i.e.

k 1 + Iog2 N. (3) Expression (3) shows the required number of ROMs with the address part in (N + 1) bits (from 0 to N) to implement the square root function with an error of 0.5 for all possible given

case of numbers. Expression (3) does not take into account the fact that the severity of the square root value may exceed the width of the data lines of the ROM. This case depends on the organization of the ROM memory.

In the example described above, a ROM with the organization of a 2K x 8, N 10 memory is selected. With this ROM, you can realize the square root function for all numbers up to 2N 20, the number of ROM being k 1 + IOQ2 10 5 without accounting data line extensions. The speed increase in the proposed device is achieved by using a ROM programmed as a function of the square root of the address value D V | AI. Thus, the computation time here coincides with the sampling time of the ROM and for mass ROM it is 100 ... 500 not.

The increase in reliability is due to the fact that the device circuit lacks any kind of counters, triggers and other elements that require special measures for noise immunity. The number from which the square root is extracted is the direct address of the ROM in which the result is programmed.

Claims (1)

The invention The device for extracting the square root, containing the first and second registers, the control input of the last of which is connected to the output of the delay element, characterized in that, in order to increase the speed and reliability of the calculations, a group of six memory blocks and a block are entered into it read control, containing a decoder and four elements AND PI, and the device start input is connected to the input of the delay element and the control input of the first register, the information input of which is connected to the information device inputs, and the bit outputs from zero to ten with the corresponding address inputs of the first memory block, the bit outputs from the fifth through the fifteenth of the first register are connected to the address inputs of the second memory block, the bits output from the eighth to eighteenth - with the corresponding address inputs of the third and fourth memory blocks, and the outputs of bits from the ninth to the nineteenth - with the corresponding address inputs of the fifth and sixth memory blocks, the bit outputs of the first, second, third and fifth memory blocks edineny interconnected and connected to the corresponding bit inputs dnym second register, and the outputs of the first the second low-order bits of the fourth and sixth memory blocks are interconnected and connected to the inputs of two high-order bits of the second register, respectively; - with the inputs of the second element OR, the outputs of the first and second elements OR are connected to the first and second inputs of the decoder, respectively, the third input of which is connected to the output of the nineteenth the bits of the first register, the first and second outputs of the decoder of the read control block are connected to the read resolution inputs of the first and second memory blocks, respectively; the third and fourth outputs are connected to the inputs of the third OR element, the output of which is connected to the read enable input of the third and fourth memory blocks The outputs of the decoder from points five to eight are connected to the inputs of the fourth OR element, the output of which is connected to the read enable inputs of the fifth and sixth memory blocks.