SU1621036A2 - Device for visual check of program execution - Google Patents

Abstract

The invention relates to automation and computing and can be used to debug programs in real time. The purpose of the invention is to improve the accuracy of the control. The device contains registers 1, 4, 5 and 6, a mode setting and address block 2, a multiplexer 3, a comparison block 7, converters 8, 13 code-voltage, an indication block 9, a linearly varying voltage generator 10, a counter 11 and a decoder 12. The purpose of the invention is achieved by forming a scale scale on the display unit, with which the operator quickly finds errors when debugging programs. 2 Il.

Description

The invention relates to automation and computer engineering and can be used to debug programs in real time.

The purpose of the invention is to increase the accuracy of control.

Figure 1 shows the structural diagram of the device; figure 2 - scale scale of the display unit.

A device for visual control of program execution contains register 1 of the current address, unit 2 for setting modes and addresses, multiplexer ί3, register 4 for the start address, register 5 for the end address, register 6 states, unit 7 for comparison, the first converter 8 code is voltage, block 9 indication , a linearly varying voltage generator 10, a counter 11, a decoder 12, a second code-voltage converter 13. In addition, in FIG. 1, the address bus 14, the device synchronization input 15, the status signal input 16, the first 17 and second 18 horizontal deviation inputs of the indication unit 9, the first 19 and second 20 vertical deviation inputs of the block are indicated. 9 indications, information outputs 21 of block 2, first 22 and second 23 output. block 2, control input 24 of multiplexer 3.

Register 1 of the current address is designed to store the current address at the moments determined by the pulses from the multiplexer 3. Its capacity corresponds to the capacity of the bus address of the computer. Unit 2 sets the mode and address is used to set the address, control registers 4 and 5, the multiplexer 3. The multiplexer 3 is designed to generate control pulses during program execution.

Registers 4 and 5 of the start and end addresses store the corresponding addresses defining the beginning and end of the program fragment of interest to the operator.

The 6 state register is intended for storing information characterizing the state of the processor (selecting a command from the ROM, accessing the stack, accessing external devices, etc.).

Comparison unit 7 compares the codes of the current address t with the codes of the start and end addresses · ^λ owls and generates a rectangular pulse whose duration corresponds to the time of the program fragment being checked. The first converter is 8 code - voltage is designed to convert the code of the current address into an analog signal. The indication unit 9 serves to graphically display the execution of programs on the first ray and the scale scale on the second ray. The linearly varying voltage generator 10 serves to create a vertical scan of the first beam of the indicator 9 and generates a sawtooth voltage pulse, equal in duration to the output pulse of the comparison unit 7. The binary counter 1I counts the current addresses of the executable program. Decoder 12 is used to convert binary code 'labels into positional code. The bit depth of the binary counter and decoder is determined by the required length of the maximum selected program fragment. The second Converter 13 code - voltage is designed to convert the positional code labels in the analog signal.

When a pulse signal appears at the output of block 7 for comparing the pulse, the duration of which is equal to the enumeration time of addresses from the start to end addresses of the selected program fragment, the linearly varying voltage generator 10 generates a sawtooth voltage pulse equal in duration to the output pulse of the comparison block 7. This sawtooth pulse is fed to the first input of the vertical deflection of the display unit 9. With the sequential (without transitions) execution of program fragments on the first ray of the indication unit 9, a straight inclined line will be observed.

When executing programs with transitions inside the selected fragment, the corresponding program pattern will be observed on the first ray of the display unit 9.

The binary counter 11 is reset to zero by the signal from the output 7 of the comparison unit. During the execution of the selected fragment of the program, the zeroing signal is removed and the counter 1 1 counts the pulses from the output of the multiplexer 3, corresponding to the change of addresses of the executed io1621036 grams. From the output of the decoder 12, strobe with the same pulses, the signals corresponding, for example, to codes 5, 10, 20, ..., are fed to the inputs of the second code converter 13 — voltage along with the pulses from the output of multiplexer 3.

So, if the inputs of the converter 13 receive signals from the output of the multiplexer 3 and the decoder 12, then 'with the appropriate choice of the operating mode of the converter ¹ 13, a scale scale similar to the divisions on the scale bar will be observed on the second beam of the display unit 9 (Fig. 2).

The large-scale cabinet on the second beam of the display unit 9 makes it easy to determine the stop address or incorrect branch of the program execution without repeatedly setting the starting address of the program. Since the executable program may have access to ROMs, external devices, standard subprograms, the scale along the vertical axis of the known device and the horizontal axis of the proposed device of the indicating unit 9 will be uneven, however, in the proposed device, the addresses of incorrect program execution are determined using scale marks definitely.

Claims (1)

Claim Device for visual control of program execution according to ed. No. 1260964, characterized in that, in order to increase the control accuracy, a linear variable voltage generator, 15 counter, a decoder and a second code-voltage converter are introduced into it, the output of the comparison unit being connected to the counter zeroing input and through a linearly varying generator. 20 voltages - with the first inputs of the vertical deflection of the display unit, the multiplexer output is connected to the counting input of the counter and the clock inputs of the decoder and the second converter 30 is connected to the inputs of the second code-voltage converter. I I