SU1201864A1 - Device for checking working skills of operator of automated control system - Google Patents

Abstract

1. A DEVICE FOR CONTROL OF PROFESSIONAL SKILLS OF THE OPERATOR OF AUTOMATED CONTROL SYSTEMS, containing the pulse distributor, the first, second, third, fourth, fifth and sixth inputs of which are connected respectively to the first and second outputs of the standard reference unit, the operator console and the comparison comparator, the first and the second The second inputs of which are connected to the third outputs of the operator’s console and the unit for setting standards, the seventh input of the pulse distributor is connected to the fourth output of the operator’s console, the first output is connected to the first the inputs of the OR element and the unit for setting standards, the second, third, fourth, fifth, sixth, seventh, and eighth outputs, respectively, with the first input of the operator’s console, the first, second, third, and fourth inputs of the counter unit, the second input of the operator’s console, and the fifth the input of the counter block, and the ninth output with the second input of the OR element, the third input of the operator’s console and the sixth input of the counter block whose output is connected to the input of the evaluation unit, the output of the Or element connected to the generator input, the output of which is connected to the second input the set of standards and the fourth input of the operator's console, the fifth output of which is connected to the third input of the set of standards, characterized in that, in order to improve the accuracy of the device, an address comparison block is entered into it, the first and second inputs of which are connected respectively to the fourth output of the block setting standards and the sixth output of the operator's console, and the first and second outputs - with the eighth and ninth inputs of the pulse distributor, respectively, the pulse shaper, the first and second inputs of which are connected respectively Reliable to the tenth and eleventh outputs of the pulse distributor, and the first and second outputs to the tenth and eleventh inputs of the pulse distributor, and the register, the output of which is connected to the fifth input of the operator console, and the first, second and third inputs, respectively, to the ninth and the twelfth outputs of the pulse distributor and the fifth output of the unit for setting standards, the fourth and fifth inputs of which are connected to the thirteenth and fourteenth outputs of the pulse distributor, respectively. S (L 2. The device according to claim 1, characterized by the fact that in it the pulse distributor contains sequentially connected clock generator, an additional register, a decoder, the first key block, the second key block and the block of elements OR, first, second, third and fourth outputs which are connected respectively with the second, Yu third, fourth and fifth inputs of the additional register, the second, third, fourth, fifth and sixth inputs of the first key block are the first, second, 00 second, sixth, tenth and eleventh respectively: the second, third, 4th, fourth, fifth, sixth and seventh inputs of the second key block are the third, fourth, fifth, sixth, eighth and ninth inputs of the distributor, respectively, and the input of the clock generator is the seventh input of the distributor, the first the second and third outputs of the decoder are the ninth, tenth and eleventh outputs of the distributor, the second, third, fourth and fifth outputs of the first key block, respectively, the sixth, seventh, eighth and twelfth outputs of the distributor, the second output of the second block of the key

Description

whose is the third output of the distributor, the third output of the second key block is the fifth and thirteenth output of the distributor, and the fifth, sixth, seventh and eighth outputs of the block of OR elements are the first, second.

the fourth and fourteenth outputs of the distributor, respectively, the second and third inputs of the OR element block are connected to the corresponding outputs of the decoder and the first key block.

The invention relates to automation and computer engineering, in particular to technical training aids, and is intended to monitor the activity of an operator of automated control systems. The purpose of the invention is to improve the accuracy of the device to increase the reliability of the assessment of the operators by increasing the classification structure of the operator's erroneous actions and eliminating the false appearance of classification signs.

FIG. 1 shows the structure of the device; in fig. 2 is a diagram of a pulse distributor entering this device.

The device contains a control node 1, a reference memory node 2, a display node 3, a response input block 4, a response memory block 5, a response comparison block 6, a generator 7, an OR element 8, a reference address counter 9, a response address counter 10, a block 11 determine the end of responses, the operator panel 12, the unit for setting standards, the node 14 for determining the end of the presentation of the standard, block 15 of counters, block 16 of evaluation (calculating the professional characteristics of the operator), counters 17-19, reversible counter 20, circuit 21 of detection zero , register 22, address comparison block 23, generator 24 the documentary pulse triggers 25-28, decoder 29, keys 30 to 44, OR elements 45-52. In this case, generator 24, triggers 25-28, decoder 29, keys 30-44, and elements 45-52 are the pulse distributor 53, the counter 20 and the circuit 21 are pulse shaper 54 (error group highlighting), triggers 25-28 are an additional trigger 55, keys 30-36 and 37-44 - in blocks of keys 56 and 57, and elements 45-52 - in block 58 of the elements OR.

The device works as follows.

On commands from node 1, test messages from node 2 are transmitted to node 3. As a test message, there can be a sequence of any characters, limited to the sign "End. The operator visually reads from the node 3 the presented information and enters the answer with the help of block 4 into block 5. According to the signal entered by the operator, corresponding to the sign of the sign “End,

generator 24 is started and a number of pulses are generated. The first generated pulse gates the passage of the signal from the output of the decoder 29 to the counters 10: -19, the register 22 and through the element 45 to the counter 9, which are then set to zero. At the same time, the signal from the output of the decoder 29 through the element 52 enters the input of the trigger 28, which is set to the one state by the second gating pulse, and generates a signal which, from the output of the associated decoder 28 of the decoder 29, enters through the element 46 to the summing input of the counter 9, thus increasing by one the address of the readable signal of the reference from node 2. At the same time, the signal from the output of the decoder 29 through the element 51 enters the input of the trigger 27, which generates a signal by the next gating pulse, which through the descrambler 29 from his third exit, element 47

arrives at the summing input of the counter 10, thus increasing by one the address of the readable response signal from the block 5. At the same time, the signal of the element 47 through the element 8 starts the generator 7,

5 by signals from which information is read from node 2 and block 5 by addresses formed respectively in counters 9 and 10. The read information enters block 6, where the identity of the information — the standard with the information — response is determined. The identity of this information leads to the formation of a signal, which by the second input prepares the key 41 for operation. Accordingly, the signal from node 14 prepares the key 32 for operation, and the similar signal from block 11 is key 38. The signal of equality of addresses of the read information of the standard and the response generated by the block 23 prepares a key 42 for operation. On the next gating pulse, the signal generated in decider 29, from its fourth output through public keys 32, 38, 41 and 42, and element 52 is fed to the input of trigger 28, preparing By thus detecting device identity information comprised within the memory and reference memory responses

5 at the following addresses. The non-identity of this information leads to the formation of a signal by block 6, which prepares a key 40 for the second input. The signal from the fourth output of the decoder 29 through the public keys 32, 38 and 40 and the element 51 are fed to the trigger input 27, which by the next the strobe pulse is generated by a signal which, through de-digitizer 29, element 47 increases by one the address of the readable response signal from block 5, thereby preparing the device for determining the identity of information — the standard and with information - the answer. Non-identity leads to further information shift — a response in the positive direction, until a signal is generated from block 11, which, through the public key 37, goes to the summing input of counter 17, thereby fixing a skip type error. At the same time, the signal from the key 37 through the element 48 is fed to the subtracting input of the counter 19, thereby eliminating the false fixation of a permutation type error. From key 37, through element 52, the signal enters the input of trigger 28, preparing the device for finding out the identity of information stored in the standard memory and in the memory of answers at addresses increased by one. The signal formed in block 23 opens the key 43. The identity of this information leads to the formation of a signal by block 6, which prepares the key 41 for operation on the second input. The signal from the output of the decoder 29 via the public keys 32, 38, 41 and 43 goes to a summing input of counter 19, which, in the absence of an error such as a pass or an unnecessary action, fixes an error such as a permutation. At the same time, the signal from the key 43 causes the code from the counter 9 to be transmitted to the register 22, and also this signal through the element 50 enters the input of the trigger 26, which forms the signal through the next gate gate in the decoder 29 through the element 46 (the summing input of the counter 9 and through the element 47 to the same input of the counter 10. At the same time, the identity of the information read through the generated addresses is detected. At the same time, the signal from the output of the debristor 29 goes to the summing input of the counter 20, which fixes a group of error-free The fact of error detection is determined in this mode by the presence of a signal from block 6 when comparing the shifted information. The error signal from block 6 opens the key 30. The signal from the output of the decoder 29 through element 50 and through element 52, respectively, goes to the trigger inputs 26 and 27 , preparing the device for the arrival of the next gate pulse, which at the next output of the decoder 29 receives a signal passing through the public key 33 to the register 22, transmitting the signal contained therein

code into counter 10. At the same time, the signal from key 30 through element 50 enters the input of trigger 26, and through element 51 to input of trigger 27, thus preparing the device for the arrival of the next gate pulse, which at the next output of the decoder 29 appears , setting to zero the counter 9 and entering through the elements 50-52, respectively, to the inputs of the flip-flops 26-28, thus preparing the device for the arrival of the next gate pulse, which at the next output of the decoder 29 has a signal that uschestvl shift information is a reference in the positive direction is detected and its identity information reply. At the same time, the signal from the next output of the baffle 29 through the element 49 enters the input of the trigger 25, preparing the device for the arrival of the next gate pulse. In case of non-identity of information and occurrence from node 14 of the signal that opens the key 33, upon receipt of the signal from the next output of the digester 29 through the public key 33 to the summing input of the counter 18, the fact of detecting an error of the excess type is recorded. At the same time, the signal from the key 33 through the element 48 is fed to the subtracting input of the counter 19, thereby eliminating the false fixation of a permutation error. The signal from the output of the decoder also enters through element 52 to the input of the trigger 28, and from the output of the key 33 (in the presence of identity - from the output of the key 39) through element 49 - to the input of the trigger 25, preparing the device for the arrival of the next gate pulse, according to which The tenth output of de-bifurcator 29 through element 47 enters the summing input of counter 10, preparing the device to find out the identity of the response information located at the address increased by one. At the same time, the signal from the next output of the decoder 29 is fed to the subtracting input of counter 20 and through elements 49 and 51, respectively, to the inputs of flip-flops 25 and 27, preparing the device for the arrival of the next gate pulse, according to which the signal from the next output of the decoder 29 in the case of a code in the counter 20 through the public key 35, the elements 50 and 51, respectively, are fed to the inputs of the flip-flops 26 and 27, thereby preparing the device to check for errors such as extra action. In case of zeroing of the counter 20, the signal from the next output of the decoder 29 through the public key 31 passes to the counter 10. By this command, the data of the counter 10 is read into the counter 9, thereby setting the same addresses of the compared information. At the same time the signal from the key 31 through the element 52 is fed to the input of the trigger 28, preparing the device to check the presence

all considered types of errors on the information remaining in the benchmark memory. The signal "End from the output of node 14 through the open with a signal from the output of the decoder 29 key 36 reads the readings of counters 17-19, which are received in block 16, as well as by the signal" End all memory elements in the device are zeroed. In block 16, the professional characteristics of the operator are calculated, namely, the probability of making mistakes and the performance of the work using various formulas to estimate the likelihood of making mistakes such as permutation, omission of action and unnecessary action.

Thus, the proposed device provides an increase in the reliability of the assessment of the operator’s performance, making it possible to eliminate errors in the assessment of the operator’s performance by taking into account not only single

errors such as skipping and unnecessary actions, but also taking into account groups of errors such as skipping, unnecessary actions and rearrangements

The invention improves the quality of experimental studies of the influence of engineering and psychological factors on the operator’s professional characteristics and can be used for professional selection. Due to the increased accuracy of control and reliability of the assessment of the degree of preparedness of operators and their knowledge, the costs of training and controlling operators are reduced.

In addition, the proposed device allows to reduce the costs, time and labor for the development of new technical means through the integrated automation of engineering and psychological research.

Claims (2)

1. DEVICE FOR CONTROL OF PROFESSIONAL SKILLS OF THE OPERATOR OF AUTOMATED CONTROL SYSTEMS, containing a pulse distributor, the first, second, third, fourth, fifth and sixth inputs of which are connected respectively to the first and second outputs of the reference unit, the operator panel and the response comparison unit, the first and second the inputs of which are connected to the third outputs of the operator panel and the reference unit, the seventh input of the pulse distributor is connected to the fourth output of the operator panel, the first output to the first inputs OR element and reference setting unit, the second, third, fourth, fifth, sixth, seventh and eighth outputs, respectively, with the first input of the operator panel, the first, second, third and fourth inputs of the meter block, the second input of the operator panel and the fifth input of the meter block and the ninth output - with the second input of the OR element, the third input of the operator panel and the sixth input of the counter unit, the output of which is connected to the input of the evaluation unit, the output of the OR element is connected to the input of the generator, the output of which is connected to the second input of the back unit reference standards and the fourth input of the operator console, the fifth output of which is connected to the third input of the reference unit, characterized in that, in order to improve the accuracy of the device, an address comparison unit is introduced into it, the first and second inputs of which are connected respectively to the fourth output of the reference unit and the sixth output of the operator console, and the first and second outputs with the eighth and ninth inputs of the pulse distributor, respectively, a pulse shaper, the first and second inputs of which are connected respectively to ten th and eleventh outputs of the pulse distributor, and the first and second outputs to the tenth and eleventh inputs of the pulse distributor, and a register whose output is connected to the fifth input of the operator console, and the first, second and third inputs, respectively, with the ninth and twelfth outputs of the pulse distributor and the fifth output of the reference unit, the fourth and fifth inputs of which are connected to the thirteenth and fourteenth outputs of the pulse distributor, respectively. 2. The device according to π. 1, characterized in that <that it contains a pulse distributor; there are sequentially connected clock generator, additional register, decoder, first key block, second key block and block of OR elements, the first, second, third and fourth outputs of which are connected respectively to the second, third, fourth and fifth inputs of the additional register, second, third , the fourth, fifth and sixth inputs of the first block of keys are respectively the first, second, second, sixth, tenth and eleventh inputs of the distributor, the second, third, fourth, fifth, sixth and seventh inputs of the second block of keys she - the third, fourth, fifth, sixth, eighth and ninth inputs of the distributor, respectively, and the clock generator input is the seventh input of the distributor, the first, second and third outputs of the decoder are the ninth, tenth and eleventh outputs of the distributor, second, third, fourth and the fifth outputs of the first block of keys, respectively, the sixth, seventh, eighth and twelfth outputs of the distributor, the second output of the second block of keys is the third output of the distributor, the third output of the second block of keys is the fifth and thirteenth outputs of the distributor, and the fifth, sixth, seventh and eighth outputs of the block of OR elements by the first, second, fourth and fourteenth outputs of the distributor, respectively, the second and third inputs of the block of OR elements are connected to the corresponding outputs of the decoder and the first block of keys.