SU1606962A1 - Digital chronometer system - Google Patents

Abstract

The invention relates to single time systems and can be applied to objects using accurate time information. The aim of the invention is to improve the accuracy of the formation of temporal information by the chronometric system by introducing a leading edge in the primary clock, the input of which is fed to the unitary time signal at a stable frequency, and the signal from its output synchronizes the counting and transmission of information to the secondary clock, in addition, synchronizes information transmission allows additionally introducing into the system a time interval meter for counting time intervals with an accuracy corresponding to the stability of the input uni Nogo signal. 2 Il.

Description

The inference is related to single-time systems and can be used on objects that use accurate time information.

The aim of the invention is to improve the accuracy of the formation of time intervals.

Figo is a structural diagram of the system; on - diagram of the address shaper and pulse bursts

The system (FIG. 1) consists of a primary clock 1 containing sequentially connected oscillator 2, divider 3 frequencies, scaling circuit 4, switch 5 and kodas converter 6. The system also includes a leading edge driver 7, an address driver 8 and bursts of pulses and communication channel 9 with secondary clocks 10 connected to it and secondary time meter 11, containing series-connected blocks

12 clock selection counter 3 of acceptable tolerance, time counter 14 and indicator 15, as well as the envelope selection circuit 16, input bus 1 7 and two control buses 18 and 19,

The output of the frequency divider 3 is connected to the input of the address generator 8 and the pulse bursts connected by its output to the address input of the switch 5, the output of the allocation unit 12 of the clock and commercial pulses is connected to the input of the extraction circuit 16, the output of which is admissible of the error connected by its control input to the first control fault 18g. The control bus 19 is connected to the reset input of the time counter 14, and the input Inna I7 is connected to the communication channel 9.

ABOUT

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The shaper 8 addresses and bursts of pulses (see Fig 2) contains a series-connected counter 20 bubble 20, a counter 21 of the number of pulses per pack, a counter 22 packs, AND 23 circuit one-shot 24 Count counts of counters 20 and 21 combine between themselves and are input shaper Sj which is connected to the output of the divider: with Zo The output of the counter 20 is connected to its counting resolution input, and the inverse resolution enable input 21c, the output of the one-shot 24 is connected both to the counting input of the counter 22 packs and the first reset input of the counter 20, the second inputthe reset input of counters 21 and 22 are combined with each other and are input shaper 8, which is connected to the output of the front edge 7 is also connected with the reset input

the divider 3 and the input of the mold 7 is connected to the input of the primary clock: the formation outputs of the counters 21 and 22 are the output of the driver 8 ,. connected to the address input of the switch 5, on the information inputs:; which contains constant batch address codes and variable time information codes from the output of the inter-: counting circuit 4 (FIG.) Circuit input: 16 selection of the bending meter 1: the intervals are connected to the output of the block; 12 clock pulses, a: the output of the circuit 16 is connected to the reset input of the counter 13 of the permissible error, the second input of which is connected to the control bus 18 of the timer 11 of the time intervals. Its second control bus 19 is connected to the reset input of the counter 14 temporarily the input bus; 17 is connected to link 9. The digital chronometric system: ma works following way

The input signal of a stable frequency of 0.5 Hz is fed to the input of the primary; clock (IF) and the input of the shredder 7, the output of which is short-pulse is generated. This pulse zeroes the counters of the driver 8 and the divider 3. The counting signal at the output of the divider 3 also, like the input signal, has a frequency equal to 0.5 Hz, and on the falling edge the time is counted by the recalculating circuit 4 o Since the divider 3 is impaled with pulses coinciding with them (with the leading edge of the input signal of a stable frequency j, the period

between the back edges of the counting pulses, the divider will also be stable. Thus, the time can be read with an accuracy that depends on the stability

ten

is

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input signal

The signal from the output of the divider 3 frequencies in the scaling circuit 4 results in counting of the following time functions: the current time in seconds, minutes and hours, the time of continuous operation in hours and days, calendar data in days, months and years All times from units of seconds before; ten years are counted in 2-10 code (for universality 4-bit) and each time function is a parallel 24-bit code that is fed to the information inputs of the collector 5 o Before the code of each time function on the information inputs KOMMjfTaTOpa The fixed 8-bit address code is set to the signal. The intermediate frequency signal is 40 kHz (T 25 µs), from the output of divider 3 (clock pulses) is fed to the counting input of the counters of the shaper 8 set to zero state ; gate 7o The zero code from the outputs of counters 21 and 22 is fed to address j input of switch 5 and connects to its output the first digit of the address code of the first time function of the current time. It prohibits the formation of the current part of the bipolar code. After the pulses (pause 8T) j received at the counting input of the counter 20, a high level of the signal appears at its output which prohibits the response to the following clock pulses. decides - the counter 21, and also permits passage of clock pulses through AND circuit 23 to the code converter 6

One clock pulse by converter b forms one bit of bipolar code, which consists of two parts, currentless, coinciding with a low level of clock pulse and a current positive (logical 1) or negative (logical O) depending on the signal level from the switch output 5 S coincident with high clock, 32 clock pulses

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0

. The state of the 5-bit counter 21, Tooeo changes the code at the address inputs of the switch and at its exit, the signals of 8 address bits and 24 bits of the current time code that appear at the information inputs switch 5, these signals are converted in block 6 to a serial bipolar 32-bit current time code (TV). After the 32nd clock pulse, the counter 21 is set to zero state, and on the falling edge of the signal from the 5th bit output meter - runs a 24 V one-shot the signal from the one-shot output sets the counter 23 to the first state and zeroes the counter 20 "

Next, a signal from the output of the counter 20 forms a pause of 8t duration, and then the unit switches the signals of the next 32-bit code and converts them by the block 6 to the serial bipolar 32-bit continuous operation time code (VNR). the primary clock generates a calendar data (CD) code. When the counter 22 is set to the third state, the address inputs of the switch 5 contain codes for which there are no data inputs, and the output of the switch is zero signal level lao In this case, the converter 6 generates a serial bipolar code with logical zeroes in all 32 bits (zero code). The next state of counter 22 is zero, and the primary clock again generates the TV code. 32-bit bipolar codes of TV, VNR CD and zero with pauses between them with a duration of 8To. At a frequency of clock pulses equal to exactly 40 kHz, exactly 500 such codes will be formed from the output of block 7, after which pause will begin before the code TVO

If, for example, the frequency stability of oscillator 2 is equal to minus, then the period of the clock pulse will be longer by μs and during the time of two pulses from the output of block 7, equal to 500 ms, 499 integer codes and 30 bits of the zero zero code will be generated. After this, the counters

1606962

20-22 will impulse with a pulse from the output of block 7 and a pause will begin to form before the TV code.

If the frequency stability of oscillator 2 is + 10, then 500 codes will be formed within 500 ms and the beginning of a pause with a duration of 2T. Then, counters from block 8 are nullified from the output of block 7 and the pause with a duration of 8T (total duration of the pause of UT) and TV code

The information from the recalculated .cxeNbi 4 also changes depending on the instability of the generator 2 either at the moment of transmission of the last two bits of the 500th zero code (zeroing the divider with 3 sh-shulk — with the former 7) or at the moment of the start of the pause before the TV B code in both cases, the time between the end of the transfer of the changed information and the moment of action

her significant change is the same

with the leading edge of the input stable signal (pulse from the output of block 7), is constant and equal to I ms for the TV code, 2 ms for the HHP and 3 ms for the CCh B code, the rest of the time between the pulses from output 7 in the codes is repeated , the information;, - Thus, the synchronization of the work of the delight 3 and the driver 8 j pulses coinciding with the leading edge

The volume of the stable input signal causes the error caused by the instability of the frequency of the generator 2 to not accumulate over time and the primary clock generates and transmits the time information with an accuracy determined by the instability of the frequency of the input signal

To set the time after switching on the primary clock, all time must be preset, except for seconds. Seconds are transmitted by time signals transmitted, for example, by radio. After the first signal, a signal is sent to the counter of seconds. This signal is taken at the sixth signal that coincides with the start. Hours are the leading edge of the input signal, the stable frequency, which is also allocated from the signals of the exact time and frequency Since the front of the counting signal from the output of the dopitel. 3, which was produced by the seconds with scheme 4, occurs with the leading edge of the input

signal of a stable frequency, then first after resetting the seconds counter, the information in the current time counter will change ovally after 1 s (after two pulses with divider 3) the sixth field of the exact time signal coinciding with the start of the hour

The time information is transmitted by the primary clock over channel 9 of communication in the form of consecutive bipolar codes (it may be perceived by clock 10 set to receive one or another time function. Secondary hours analyze the address part of all 32-bit codes and Its coincidence with the established rep Accept the information part of this code for the p Next processing

32-bipolar sequential bipolar codes ,. present in the canap

connection; The THJCsce is used with a 1 time interval meter for obtaining br-sh stable counting pulses at a fractional time interval W: approx. 1.2 spacing of the clock pulses of the meter 1 1 converts continuous bipolar signals. codes in packs of 32 monopolar pulses LH pulses, similar to the packs at the output of circuit 23; the imager has 8 primary clocks o On the front / front of the first impulse, the envelope selection circuit 16, the output of which appears low and keeps while the meldzu has two adjacent clock pulses of no more than 25 xx. This signal allows the counter Oj to work and if the control signal level is present on the control bus 18, the counter starts counting the tal; but the counter 20 fordovatap the inverter and works as follows

With the presence of low (permissive) signal levels at the reset inputs and at the control input, the Pmzmeg counter: emits the status at its outputs to the rear, non-M; f, to the front of the clock impulses sent to the clock input By the back- / front of the eighth impulse produced; - the high level of the signal at the output of the counter is locked and the counter is locked at the control input. On the leading edge of this signal, counting is performed in counter 14, which is set to zero level high. manager sig

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on the second control input of the interval meter, and the information from counter 4 is displayed on the 15 o indicator. Counter 13 is zeroed (set to the initial state) by a signal from the output of the 16 o block. Thus, the period of the counting signal dc of counter 14 is equal to the period between back edges the eighth clock pulses of two adjacent packs from the output of block 12 o

The number of counting signals in a time of 500 ms is equal to 500. The choice of the eighth clock and ipylca allows the generator 2 to be used in the system with an instability value of up to 8 O.5, and the accuracy characteristics of the iivibi system remain with

0

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five

0

When the generator instability 2 is not npeBbuJJamiLieJi {8-10, 500 whole codes will generate 500 whole codes3 a pause of 8T duration and no more than 8 bits of the next TBO code. Then again a pause of 8T duration and a TB code are generated. In the meter 1 I LR-GSHN 50 f; The mu for the period of 500 ms of the input stable signal is not generated and the secondary clock does not start receiving the information part of the TBO code Only with a further deterioration of the instability, the frequency converter will form a specific and several bits of the information part of the TV code, and the second is less. will receive the information part of the current time code; 1and, which will terminate in the synchronization of the primary clock by a jvieHT. pulse from the forwarder 7 Toyo at this moment in the secondary clock will be a failure of information about the current.

Thus, for a stable time interval of 500 ms, a constant number of counting pulses is formed for a counter of 14 time intervals. thus, the accuracy of the time intervals is ensured; the ball depends on the stability and the input signal-structured strength. at usual instability. small-sized generators + 10 will be equal 50 mkso

In general, in the form of a counting signal, it’s not the eighth but any other impulse of the packet, taking into account the characteristic dp 1 of the generator 2, the frequency,

Claims (1)

Digital chronometric systems containing primary clocks, including series-connected Topj frequency divider, scaling circuit, commutator and code converter, address generator and pulse bursts, one input connected to another frequency divider output - control input with switch qi The code converter associated with the output with the output of the primary clock, connected through a communication channel to the secondary clock, is characterized in that, in order to improve the accuracy of forming the time and formation primary clock synchronized vtsde formed in a first level secondary clock, which is entered in the leading edge generator, coupled to the input signal time stable ten frequency of the system, while the output of the front-end former is connected to another input of the frequency divider 5 and the second input of the address former and bursts of pulses, the other output of which is connected to another input of the code converter, and a secondary interval meter is introduced into the system time of the second level, made in the form of sequentially I connected to the block of the allocation of pulses of pulses, the permissible error counter, time counter and indicator 5 pa, as well as the envelope circuit, which is turned on by the output of the block dividing the clock pulses and the installation input into the permissible error counter, the control input of which is connected to the first control bus, the second control bus is connected to the reset input of the time counter and the input bus to the communication channel. FSh.2