SU1605212A1 - Distributed system for program control of production processes - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in programming controllers, machine tools with numerical control, process control systems. The purpose of the invention is to expand the scope of the system based on an increase in the number of exchange interactions. The distributed system comprises ^N. M channels, each of which contains a program memory block, an address switch, an address register, a command register, a logic conditions multiplexer, a synchronization block, an AND block, an I. 3 hp f-ly.

Description

The invention relates to automation and computing and can be used in distributed software control systems, programmable controllers, machine tools with numerical control, automated control systems of technological processes.

The purpose of the invention is to expand the scope of the system based on an increase in the number of exchange interactions j

The essence of the invention consists in the following,. The distributed system for software control of technological processes consists of a plurality of similar modules (channels) combined into a matrix

 structure. Each individual module of the system controls a certain group of technological processes that form the software control level. The set of control programs executed by the channel consists of two subsets of the M and Mj commands. The first type of commands is intended directly to control the corresponding technological process.

During the execution of the program, the channel can force into one of two directions commands of the second type M, which form exchange commands (transfer of control). The format of this command is

about:

about

SP

to

N3

etc

four

m

k

where ra is the number (code) of the receiver channel

 information;

m is the number (code) of the program that the receiving channel must perform with

Each channel that is part of a distributed system is assigned its own number (identifier), which determines its location in the matrix horizontally and vertically. The exchange of control transfer commands can be made either by a row of channels or in a column. The lines and columns of the channels form a ring structure, which ensures the full implementation of the full interaction of the individual channels, i.e., the implementation of the discipline, each with each

Upon receipt of a message from a neighboring channel, it is determined whether the received information is intended for it. This occurs by comparing the receiver's channel codes (channel identifier) with the address part of the message

If the codes do not match, the message is sent to the adjacent channel and the ToDo until the codes match either in the column or in the channel row. If one of the two codes coincides, the message propagation direction changes.

The introduction of an analysis unit is necessary to implement the procedure for identifying the information received and choosing to further advance it in the matrix of channels of the distributed system

The introduction of a buffer storage unit of messages is necessary for the temporary storage of program codes received for service to this channel.

The constant memory block is intended to store a single composite code defining the location of the channel in the matrix structure of the distributed system. The process of sharing information from the memory block occurs via a synchronization pulse from the distributor.

FIG. 1 shows the functional scheme of the i-th (i 1, n.xm) channel of the distributed system for software process control; in fig. 2 - functional diagram of the buffer storage unit; Figs 3 - functional block diagram

d with 2P

25

35

0

analysis; in fig. 4 is a functional diagram of the first (second, third) message memory block; Fig. 5 is a functional block diagram of the direction of information transfer; FIG. 6 is a functional diagram of the output demultiplexer; FIG. in fig. 7 is a functional block synchronization circuit; in FIG. 8, the format of the processing command (a) and the format of the exchange command (b); FIG. 9 is a functional diagram of a pulse distributor; FIG. in fig. 10 - time diagrams Functioning of the pulse distributor; in fig „t1 - an example of a coded matrix of channels in a distributed system of dimension 3 X 3 and directions of transmission of exchange commands

The i-th channel of the distributed system for software control of technological processes contains a block of 1 program memory, a buffer memory unit 2 messages, an analysis block 3, a switch 4, addresses, an address register 5, a command register 6, a logic multiplexer 7, block 8 synchronization, the first block of elements And 9, the second block of elements And 10, the element And 11, the first 12, the second 13 and the third .14 information inputs, the first 15 and the second 16 control inputs, the input 17 of logical conditions, the first 18, the second 19 and third 20 informational outputs

The buffer storage message block (BZB) (FIG. 2) contains information output 21, switch 22, demultiplexer 23, register block 24.1-24.1 (where 1 is the queue depth), a group of blocks of elements of the NIS 25s, 1-25.1-1, first block elements AND 26.1-26c1, the second block of elements AND 27.1-27.1, the block of elements OR 28.1-28L, element OR 29, element AND 30, the one-shot 31,

Analysis unit 3 (Fig. 3) contains the first 32, second 33 and third 34 message memory blocks, multiplexer 35, constant memory block 36, information transmission direction selection block 37, trigger 38, buffer register 39 with 39.1 address 39.1 fields, block 40 elements And, output demultiplexer 41, demultiplexer 42 synchronization, decoder 43, counter 44, distributor 45 pulses, element 46, element OR 47 "

 The first 32, the second 33, the third 34 message memory blocks (FIGO 4) contain a block of registers 48 ,, 1-48 K (where K is the length of the message queue), a group of blocks of elements OR 49, 1, 49. (K-1), the first block of the elements AND 50о1-50оК, the second block of the elements И 51.1-51.К, the block of the elements OR 52.1-52.К, demul tighexor 53, the element And 54, the element И И НЕ 55,

The block for selecting the direction of information transfer 37 (Fig. 5) contains the first 56 and second 57 schemes, compared to the incomplete decoder 58, element I 59.

The output demultiplexer 41 (Fig. Contains the first 60 and second 61 blocks of elements Io

The synchronization unit (Fig. 7) contains a trigger 62, a clock pulse generator 63, a counter 64, a decoder 65, And 66 and 67 elements.,

Pulse distributor 45 (Fig. Contains a clock pulse generator 68, counter 69, decoder 70, control trigger 71.

The purpose of the main blocks and elements of a separate channel of a distributed system is as follows.

Unit 1 of program memory is intended for storing control commands and exchange commands (transfer of control to similar channels of the system). The buffer storage unit 2 is designed to store messages received from the service from other channels of the system and the supervisory device (central processor). The analysis unit 3 is designed to analyze incoming messages regarding the belonging of information to a given channel and select the direction of transmission during transit passing of the received message. The synchronization unit 8 is designed to generate clock pulses that synchronize the operation of the channel.

In block 3 of the analysis, the purpose of the main elements is as follows. Blocks 32-34 of the message memory are designed to store the exchange commands received for the own channel and adjacent (two) system channels (from the left one when the message is moving in the system channel row and from the bottom one when moving in the channel column). Constant memory block 36 is designed to store the channel address code identifying its location in a distributed system. Block

36, the memory of a constant can be made, for example, in the form of a series connection of a constant code generator (toggle register, etc.) and a block of elements AND, the second input of which is connected to the input of the memory block.

The information transmission direction block 37 is intended to select and modify the direction of the issue of messages depending on the ratio of the source and receiver channel codes of the community.

The buffer register 39 is designed to store the message code for the time of its analysis and processing. The output demultiplexer 41 is intended for. switching the exchange command to one of the outputs of the analysis unit 3 and the whole channel to the analogous channels of the system. The distributor 45 pulses intended for} 1 to synchronize the work unit 3 analysis. Counter 44 is a sequential ring and, in conjunction with a decimator 43, serves for sequential cyclic polling of the message memories 32-34.

In a distributed system for software process control (technological) consisting of channels of the same type (Fig. 11) control commands are exchanged in two directions. Each horizontal and vertical line of the same channels of the system forms a corresponding channel ring, which can be implemented as a separate LSI (VLSI). Then the complexing of the system will consist in the serial connection of individual VLSI systems

In the initial (initial) state, the memory elements of the system (channels) are in the zero state (with the exception of bit 6.6 of the register of 6 commands defining the end of the control program)

The operation of a distributed system for programmed control of technological processes is possible in three modes: the processing mode (in advance) of its own control commands; mode of exchange commands; mode of receiving and processing exchange commands.

Since a distributed system consists of a set of channels of the same type, we consider the operation of the system on the example of the functioning of a separate channel.

 sixteen

The signal at the start of operation comes from the control input 15 of the channel (Fig. 1) This signal goes to the control input of the synchronization unit 8 (Fig. 7) and enters the S input of the trigger 62, sets it to the O state. 63 starts to generate clock pulses for synchronization of the channel in the source connection trigger trigger 62 and the counter 64 is in the zero state. The resetting of the counter 64 in FIG. 7 is not returned.

The state of the inputs of the synchronization unit 8 in the initial state is determined as follows: The logical zero signal from the input 15 of the channel arrives at the first input of the synchronization unit 8 (FIG 1.7). The second input of the synchronization unit 8 receives a logical unit signal (a mark is a sign of the end of the program from the output of the 6.6 register 6 registers). The logical zero signal is sent to the third input of the synchronization unit 8 from the input 16. And since the buffer storage unit 2 is in the zero state, then from its control output to the fourth input of the synchronization unit the signal of the logical unit arrives.

The trigger 38 is set to the zero state by the pulse of the distributor 45 at the zero state of the registers. 48.1-48.K blocks 32-34 message memory.

In the initial state, the channel memory elements are in the zero state (with the exception of the register of 6 commands defining the end of the process control program) „

Channel operation in the processing mode of its own control commands. Channel operation in this mode of operation begins by applying to the input 12 (Fig. 1) an operation code defining the address of the first command of the control programs. This code is supplied, for example, from a dispatcher organizing a control process.

The operation code from the input 12 of the channel goes through the switch 22 of the buffer storage unit 2 messages (Figo 2) to the information input of the multiplexer 23. Since the block of registers 24,1-24.1 is in the zero state, at the outputs of the And elements 26.1-26j, l block are signals

Q

g 20 5 o

d

5 o

five

28

logical unit. These signals.,. arriving at the control (address) input of the demultiplexer 23, allow the recording of information in the first register 24.1 through the block of elements OR 25.1. Together with the program address (operation code), a control pulse is applied to the input 12 of the channel. This pulse is through the element OR 29, the element AND 27 about 1 and the element OR 28.1 is fed to the synchronizing input of the register 24.1 and records the received operational code The state of the register will be different from zero and the output of the AND 26 o 1 element will be a logical zero signal, which determines the writing of the next opcode to the second register 24 o 2 of the buffer storage unit. In the zero state j-ro (j) of the 24oj register, at the output of the element AND 26.J there will be a signal of the logical unit arriving at the corresponding input of the element 30 And therefore at the output of the element 30 there will be a signal of the logical unit only at the zero state of the block of registers 24 1 -24-01.This signal is fed through the control input of block 2 (FIG. 2) to the control input of synchronization block 8 (fig1) and thus allows the channel to be terminated when the last control command is reached (mark is a sign of the end of the program in the bob field of register 6 )about

Simultaneously with the filing of the operation code, the control input 15 of the channel (figo 1) sends a signal to the start of operation. This signal arrives at the control input of the synchronization unit 8 (figo 7), sets the trigger trigger 62 to one and thereby enables the output clock generator 63 to synchronize the operation of the channel "Synchronization of work is carried out by signals from the outputs of the decoder 65 of the synchronization unit 8

The first clock pulse from the output of the synchronization unit 8 (FIG. 1) arrives at the synchronizing input of the address register 5 and allows recording information from the output of the buffer storage unit 2 (the first register 24o 1 of the register 24.1-24o1) into it through the co-device 4 addresses “On the second clock pulse from block 1 of program memory, a command will be read, which according to clock pulse from the output of synchronization block 8 will be entered into command register 6 (the format of the counted command is shown in Fig. 8 a) o

Since there is no indication of control transfer in the register field 6 of commands, the operational part of the command from field 6 - 4 of register 6 goes through the block of elements AND 9 to the information output 18 of the channel for controlling the process, Floor 6-1, 6.2 and 6.3 register 6 commands form the address of the next command using the multiplexer 7 logical conditions, which is intended to form the value of the mode of the digitized address of the next command and implements its logical function of the form

y, x, a, x,. z

Y is the output signal of the multiplexer 7 logical conditions; i-x - conjunction cZ, oTj о о о о, corresponds to the code from the output 6o1 of the code of logical conditions, allowing the modified address bit to pass without changes;

thirty

Xg (/ (, Xj o, o; 20 (3 o 00 Olt,

4 Olt ... conjunctions, corresponding to the codes defining the passage to the output of multiplexer 7 of one of the signals of the logical conditions z, z ,,,.,. with. input 17 logical conditions of the channel conditions,

With the last command of the formed control program in the field 6.6 of register 6, a label is entered - a program termination note. This label arrives at the control input of the 4-address switch and allows information (addresses of the next program) to pass through it from the buffer memory. block 2o. In addition, this label goes to the control input of the buffer storage unit 2 (Figo 2) and forms a pulse along the front at the output of the one-shot 31. This pulse through the elements OR 28.1-28.1 goes to the synchronization inputs of the block of registers 24.1-24-1, and thereby shifts the information.

p 15 2Q

i-

thirty

35 40

is -Q If the last command was executed, the queue of requests received for servicing becomes empty (the zero state of the block of registers is 24.1-2.24.1). At the outputs of the And 26.1-2.16 elements, signals of a logical unit are formed. At the output of the element 30, a signal of the logical unit appears, which from the output of the buffer storage unit (Figo 1) is fed to the input of the synchronization unit 8 (Fig. 7). At the output of the AND 66 element, a logical unit signal is generated, which through the OR 67 element sets the trigger trigger 62 to the zero state and the channel terminates its operation.

If the queue in the buffer storage unit 2 is not empty, after the information is shifted in the register block 24 "1-24 o 1, the first clock of the next pulse sequence records information into the address register 5 and then the channel functions in the same way as before

The operation of the channel in the mode of exchanging exchange commands. In the course of processing its own commands, the channel can issue commands for exchanging other similar channels forming a bidirectional ring structure of the distributed system.

The format of the exchange command (control transfer) is presented in FIG. 8 „5. In this case, with a floor of 6.4 registers of 6 teams, the command is given

   1 to where t, .- code (number) of the receiver channel

information;

k code (number) of the program to be executed by the system channel; tt- - a sign of concatenation (deshteni), In turn

™ pr 1p „p

F m

6 pr

where m

etc

at

- channel number of the receiver information in the line of similar channels; pp channel number of the receiver

information in a column of similar channels.

Simultaneously with the code w of the exchange command, from the output of the field 6.5 of the register of 6 commands, a label is issued — a sign of the transfer of control to a similar channel.

This label enters the control inputs of the block of elements And 10 and the element 11 (fig about 1) and thus allows the exchange command from the floor 6 "4 of the register 6 through the block of elements 10 to the information input of the analysis block 3 (fig 3) o Together with the exchange command, a clock pulse is received from the output of the synchronization unit 8 via the And 11 element (FIG. 1).

The exchange of commands in a distributed system, the rest of the channels of the same type, is carried out (Fig. 11) in two directions. For each of the directions in analysis block 3, there is a message storage unit (WLAN) (FGSZ). The third BPS is designed to store exchange commands from its own channel

In this case, the exchange command is fed to the input of the BPS 32c. Since the block of registers 48.1-48.K (where K is the queue depth) (Figs 4) is in the zero state, then the outputs of the AND 50.1-50 elements. units. These signals are sent to the address input of the demultiplexer 53 and thereby permit the recording of the incoming message to the first register.48.1 of the queue.

The address of the demultiplexer 53 BPS 32-34 (figo 4) consists in the following Zero outputs of registers, K are connected to the inputs of the corresponding elements And 50.1-50. To Consequently, when i-ro (, K) is in register 48 о i in the zero state the output of the element And there will be a signal of a logical unit of g; . This signal is sent to the address input of the demultiplexer 53 and to the corresponding input of the item NAND 55 ..

In case of the 48.1-48K registers zero state, the output of the NAND 55 element will be a logical zero signal, which goes to the control output

The addressing of registers, to de-multi-steakor 53, for entering information into them is determined by the scoreboard1,

When entering information in at least one register 48oi. (, K) (iFj) at the output of the element AND-NOT 55, for example,

 Fj-F ,,,, g + will be a signal of a logical unit.

Table 1 Status code of the block re- I Addressing

gistrov

gistra (r)

to-"

R,

The state of this register (48.1) will change, and thus the second register 48.2 will be prepared to record the next message (exchange command). When writing an exchange command to the register 48 o 1, a logical unit signal appears at the output of the NAND 55 element. This signal from the BPS 32 code through the OR 47 element (fig 3) sets the trigger 38 to one and thus allows the generation of clock signals. pulses at the output of the distributor 45 to synchronize the operation of the unit 3 analyzers

The operation of the analysis unit 3 occurs in five pulse sequences (Fig. 10). The operation cycle (cycle) consists of five phases, each of which begins with a clock pulse of the corresponding pulse sequence.

The first pulse is used to access the corresponding BPS 32- 34 by increasing the content of counter 44 by one. The second pulse is used to write the message to the buffer register 39. The fourth pulse is used to send the exchange command to either adjacent channels of the system or to this channel for further processing. . The third pulse is used to access the memory block of a constant 36. The second pulse is used to shift information (exchange commands) in the BTS, from which information for analysis has been calculated. Next, the work cycle of the analysis block 3 is repeated by accessing the next message memory block.

The selection of the direction of transmission of the information is as follows.

Zomo Address part of the received message is compared with the address- (identifier) of the channel by line and column numbers, and one of the three possible directions of transmission (two to adjacent channels and the third to processing this channel) is determined according to the following rule.

I

Let A and B are codes of addresses of the source of information channel horizontally and vertically (rows and columns) of channel placement in the system, and C and D are codes of addresses of the channel of information receiver. The procedure for selecting the direction of information transfer, implemented by block 37, is determined by the table. 2

table 2

14

1, if it is required to transmit information upwards; Oh, if you want to pass in

ten

formation right Comparison signal generation by elements 56 and 57 is determined by tablo 3

Table 3

five

0

Value codes

A C

A C

A C

In d

In d

In d

Signs of Comparison

s

with

but"

In block 36 of the memory of the constant of analysis block 3 (FIGO 3), a single address code (identifier) is written, which determines the location of this channel during the matrix construction of the distributed system

When an exchange command is entered in the BPS 32, a pulse from the output of the distributor 45 increases the contents of counter 44 by one. The output for the delfrater 43 initiates a signal to interrogate the BPS 32. The code from the output of counter 44 goes to the control input of the multiplexer 35 and thereby allows recording information on to the second pulse from the BPS 32 to the buffer register 39 Based on a comparison of two channel address codes in the comparison circuits 56, 57 of the information transmission direction selection block 37 (Fig. 5) i at the output of the incomplete decoder in accordance with Table. 3 sign is formed

0

five

The generated attribute is received (FIG 3) to the control inputs of demultiplexers 41 and 42. The demultiplexer 41 determines the exchange command to one of the two directions (FIG 11) to adjacent channels. To synchronize the recording of the exchange command in the adjacent channel from the distributor 45 output, impulse C, which through Demultiplexer 42 is fed to the corresponding output

Channel operation in the mode of receiving and processing exchange commands. When processing exchange commands from neighboring channels, the corresponding BPS is accessed (33,34).

When the codes of the addresses of the receiver of the information receiver coincide with the address part of the exchange command at the outputs Equals the first 56 and second 57 comparison circuits of the block 37 (Fig. 5), the signals of the logical unit are formed, which form the signal of the logical unit at the output of the element 59. This signal from the output of the information transmission direction block 37 arrives at the control input of the AND 40 block and thereby resolves when a pulse arrives (from the output of the distributor 45, passing the operation code (starting address of the control program) from the output of the analysis block 3 to record it in the buffer memory unit 2. Next, the channel works in the same way as the one considered in re; processing its own control commands.

The end of the process of executing the channel control commands is as follows. The label — a sign of the program from the output of field 6.6 of register 6 — is fed to the control input (FIG. 1) of the synchronization signal. If the queue in the buffer storage unit 2 (FIG. O2) is empty, then the output of the element 30 is a logical unit signal. This signal from the output of the buffer storage unit 2 is fed to the triggering input of the synchronization unit 8 (FIG. ) and upon the arrival of the label - a sign of the end of the program for generating control signals - at the output of the element AND 66 a signal of the logical unit is formed, which through the element OR.67 sets the trigger 62 to the zero state, and on this the channel ends its work

Claims (1)

1. A distributed system for software process control, containing nxm channels, where n, n is the number of channels in the row of the matrix organization of the system, and m is the number of lines, and the i-th channel (i 1, n m) of the system contains program memory block, address switch, address register, command register, logical conditions multiplexer, synchronization block, first block of AND elements, AND element, the first control channel input connected to the first synchronization block input, the first output of which is connected to the synchronizing input register and the address, the output of which is connected to the input of the program memory, the output of the program memory, is connected to the information input of the command register, the synchronizing input of which is connected to the second output of the synchronization unit, the output of the field of the logical commands that are checked. the input of the multiplexer logical conditions, the output of the modifiable address of the address of the command register is connected to the second information input of the multiplexer logical conditions, the output of which is connected to the input of the modified the second bit of the address of the first information input of the address switch, the output of which is connected to the input of the modified bit of the address of the first information input switch address, the output of which is connected to the information input of the re, Q 15 20 25 30 jr 40 45 jq gf the address hub, the input of the logical conditions of the channel are connected to the control input of the multiplexer logical conditions, the output of the field of unmodifiable bits of the address of the command register is connected to the inputs of the non-modifiable bits of the address of the first information input of the switch, the output of the operation field of the command register , the output of which is connected to the first information output of the channel, the output half of the end of the program of the command register is connected to the direct and inverse control inputs s of the address switch and the second input of the synchronization unit, the second control input of the channel is connected to the third input of the synchronization unit, the second information output of the K-th (k 1, n - 1) channel -) -and () 1, t) channel row is connected to the second information input of the (K + 1) th channel of the line, the second information output of the n-th channel of the m-th line connected to the second information input of the first channel -V-line, about t and h and h that, in order to expand the field of application of the system based on an increase in the number of exchange interactions, It additionally contains a buffer message storage unit, an analysis unit, a second block of AND elements, the information output of the buffer memory block is connected to the second information input of the address switch, the output of the instruction register operating field is connected to the information input of the second block of AND elements, whose output and output of the AND element connected to the first input of the analysis unit, the control output of which is connected to the control input of the buffer storage unit, the control output of which is connected to the fourth by the synchronization unit stroke, the third output of which is connected to the first input of the AND element, the output of the control register transfer field is connected to the inverse control input of the first AND element block, the forward control input of the second AND block and the second input of the AND element, the first information output of the analysis block is connected to the first information input of the buffer storage block of messages, the output half of the program register end is connected to the second control input of the buffer storage unit of messages, the first information input of the channel is connected to the second information input of the buffer storage unit, the second information input of the channel is connected to the second input of the analysis unit, the second information output of which is connected to the second information output of the channel, the third information input of the channel is connected to the third input of the analysis unit, the third information output of which is connected to the third information output of the channel, the third information output of the j-ro (, l) channel la u-th column (front 1, p) channels connected to the third information input (j-l) -ro channel, the third information output of the first channel (V-th channel column connected to the third information input of the t-th channel of the corresponding channel column 2 o System pop ,, 1, characterized in that the analysis block contains the first - the third message memory blocks, the multiplexer, the constant memory block, the block of the direction of information transfer, trigger, buffer register, AND block, output demultiplexer , a synchronization demultiplexer, a decoder, a counter, a pulse distributor, an AND element and an OR whose output is connected to the S input of the trigger and an inverse input of the AND element whose output is connected to the R input of the trigger, is distributed to the control input The pulses, the first output of which is connected to the counter input of the counter, the outputs of the counter are connected to the inputs of the decoder and the control input of the multiplexer, the output of which is connected to the information input of the buffer register, the synchronizing input of which is connected to the second output of the pulse distributor, the third the output of the pulse distributor is connected to the input of the memory block of a constant, the output of which is connected to the first input of the transmission direction selection block, the second input of which is connected to the output ad field of the buffer register, the output of the operational field of the buffer register is connected to the information input of the block of elements I, the output of which is connected to the first information output of the block of analysis, “J pp 25 ZO Q d 35 five the moves of the address and operational fields of the buffer register are connected to the information input of the output demultiplexer, the nepBbni and the second outputs of which are connected respectively to the second and third information outputs of the analysis unit, the first to third inputs of which are connected to the information and the first charging inputs of the corresponding memory blocks messages, the information outputs of which are connected to the corresponding information inputs of the multiplexer, the control outputs of the message memory blocks are connected to the inputs of the elements This W, the fourth output of the pulse distributor is connected to the forward input of the element I and the information input of the synchronization demultiplexer, the outputs of which are connected to the corresponding information outputs of the analysis unit, the first output of the information transmission direction selection block is connected to the control input of the output demultiplexer and the synchronization demultiplexer control input , the second output of the block for selecting the information transfer direction is connected to the synchronizing input of the synchronization demultiplexer building block elements and a control and analysis unit output, a fifth output is connected to a pulse distributor taktovp br inputs of the first - third message memory blocks, the decoder outputs are connected to second inputs of the gate corresponding to the memory blocks messages  Zo System of On 1, characterized in that the buffer storage unit contains a switch, a demultiplexer, a block of 1 registers: (where 1 is the queue length), a group of. (1-1) th block of OR elements, two AND blocks, OR block, OR element, AND element and one-oscillator; whose output is connected to the inverse control input of the demultiplexer and the first inputs of the OR elements the block, the outputs of which are connected to the synchronizing inputs of the respective registers, the first control input of the buffer resembling block is connected to the forward and inverse luing inputs of the switch, the output of which is connected to the information input of the demultiplexer, Kth (1-1) j connected to the Fi9.1 Fi.g FIG. four FIG. five IF FIG. 6 7 a 5 FIG. eight 10