SU1598140A1 - Pulse selector - Google Patents

Abstract

The invention relates to a pulse technique and can be used to isolate periodic pulse signals from interference. The purpose of the invention is to improve the accuracy of selection by reducing the distortion of the pulse shape and allowing the selection of the optimal number of analyzed periods of the input signal, as well as expanding the frequency range by allowing control of the delay time. To achieve the goal, an analog-digital converter 1, switches 2, 5, the smallest value selector 3 and timer 7 are entered into the device containing the key 4 and delay unit 6. The first period of the input signal passes through switches 2 and 5 into block 6. Subsequent the input signal peridy goes to block 3, the output of which passes the coincident part of the pulses. In order to allow adjustment of the delay in block 6, processing is carried out numerically. In addition, the device includes a bus 9 sample pulses, bus 10 launch, bus 11 set the number of pulse sequences, bus 12 set the delay time, bus 13 clock pulses. 1 hp ff, 3 ill.

Description

Iff

ate

with

00 4

The invention relates to a pulse technique and can be used to separate pulse periodic signals from interference.

The purpose of the invention is to improve the accuracy of selection and the expansion of the frequency range.

FIG. 1 shows a block diagram of the device; in fig. 2 - timer circuit diagram; in fig. 3 is a block diagram of the smallest value selection unit.

The pulse selector contains serially connected analog-to-digital converter 1, the first switch 2, the smallest value selection unit 3 and the key 4, the second switch 5 and the delay unit 6 successively connected, as well as the timer 7, the input bus 8, the sampling pulse bus 9, the bus 10 start, the bus 11 set the number of pulse sequences, the bus 12 set the delay time, the bus 13 clock pulses and the output bus 14.

The first output of the first switch 2 is connected to the first input of the second switch 5, the second input of which is connected to the output of unit 3. The input bus 8 is connected to the input of the analog-digital converter 1, the start input of which is connected to the bus 9. The first timer output is connected to the control inputs of the first and the second switch 2 and 5, the second output - with the control input of the key 4, the first, second, third and fourth inputs of the timer - with tires 10-12, respectively. The second and third inputs of block 6 are re-connected with tires 12 and 9, respectively, and the output - with the second entrance Lok, 3. The output of the key 4 is connected to the output bus 14, Timer 7 (Fig. 2) contains the first

15 and second 16 triggers, first 17

and the second 18 pulse counters, the first 19 and second 20 comparators of the codes element And 21 and the one-shot 22.

The first input element AND 21 is the first input of timer 7 and is connected to the reset inputs of the flip-flops 15 and

16 and the second counter 18. The second input element And 21 is connected to the output of the one-shot 22, the installation input of the first trigger 15 and the counting input of the second counter 18. The output element

And 21 is connected to the reset input of the first counter 17, which is the counting input

0

five

0

five

0

five

0

five

It is the third input of the timer 7, and the output is connected to the first input of the first comparator 19, the second input of which is the fourth input of the timer 7, and the output is connected to the input of the one-shot 22. The output of the second counter 18 is connected to the first input of the second: comparator 20 , the second input of which is the second input of the timer 7, and the output is connected to the clock input of the trigger 16.; The delay unit 6 in the case when a variable delay is realized may be performed using one of the known controlled digital delay circuits, for example, on the basis of integrated circuits, which are a variable-length shift register.

Block 3 (FIG. 3) contains a code comparator 23, the OR element 24 and the switch 25, the output of which is the output of block 3, the first and second inputs are the first and second inputs of block 3 and are connected respectively with (The first and second inputs of the comparator 23, the first and second outputs of which are connected to the inputs of the OR element 24, the output of which is connected to the control input of the switch 25.

The pulse selector works as follows.

Before operation, the devices are set, for example, with the toggle switches on the bus 1 1, the values of the number of pulse sequences n necessary for preselection of a signal before it is input, and on bus 12 the delay time T equal to the repetition period of the sequences of pulses.

The device starts to operate on a trigger signal on bus 10, according to which Timer 7 generates control signals for switching switches 2 and 5 to the I-II contact closure position and opening key 4.

Signal from the input; devices through switches 2 and 5 enters the unit

6 latency After time O, equal to the specified delay time, timer

7, on the first output, forms a control signal that switches switches 2 and 5 to position I-III. Thus, at both inputs of the block 3 for selecting the smallest value of synchro-. but in-phase signals will come from the device and from the output of the delay unit 6 (Fig. 5a, b).

Unit 3 selects the useful signals, passes the common part to its output and three signals at the same time to its inputs, and eliminates the non-coincident interferences present in the mixture with the signal. The result of comparing the direct and delayed signals is again fed through block 6 to the input of block 3 for subsequent selection. At the same time, with each comparison cycle, in time, it is equal to the repetition period of pulse signal sequences, if

will correspond to C (N Comparator 19, producing a comparison With f-ry-H N, generates a signal of equality of codes, according to which the one-shot 22 forms a short pulse of setting the counter to the zero state 17 and to the trigger one state 15 15, which corresponds to the switching of contacts I-III of switches 2 and 5, will remain unchanged until the arrival of a new start pulse. Counter 17 will continuously continue counting and pulse f ;.

The interference of the noise transmitted to the output of the 5 D ° Shaped single-bypass 3 as a result of their random time (phase) coincidence at its inputs will steadily decrease. . After (n-1) comparison cycles, corresponding to the time (n-l), .. timer 7 on the second output causes a control signal that closes the contacts of key 4, and the processed signal will be output to the device. The number of signal preselection cycles (p-1) is chosen based on the specific interference situation by compromising the minimum signal processing time on the one hand and achieving an acceptable result in noise suppression on the other. In the absence of interference coincidence (the interference situation is easy), the passage of only two pulse sequences (), i.e. one cycle of comparison.

The possibility of varying C and p allows us to process signals with different repetition periods of pulsed-sequences and best adapt to the interfering conditions existing at a given time. When changing p and G, the device switches to a new mode of operation after a trigger signal is sent via bus 10.

Timer 7 works as follows. .

. On the trigger signal, the counters 17 and 18 and the triggers 15 and 16 are reset to zero. At the same time, the potential outputs of the trigger 15 and 16 will have zero potentials, which corresponds to the switching of the I-II contacts of the switches 2 and 5 and the open contacts of the key 4 At the end of the trigger signal, the counter 17 will begin counting with the pulse 22 the pulse is also clocking for the counter 18, which counts the number of count cycles of the Counter 17, each of which

20 duration is 1. Comparator 20 marks the point in time when the number of cycles counted by counter 18 becomes equal to the specified (n-1) Comparator codes match signal

25-20 will translate the trigger 18 into one state, which will lead to the closure of the contacts of the key 4. The cycle of the timer 7 ends.

Introduction to device-hollow

30 of the digital converter 1 is dictated by the need to process signals with a different follow-up period, which in turn requires the use of block 6 of delay c. vari

the delay time, which for analog signals is a rather complicated task, while the digitized signal can be delayed by

40 any time

To ensure synchronization, the work of the timer 7 and block 6, the frequency of the pulses on the bus 9 (f / b) clock pulses on the bus 13 (f-rtf) must

d be multiples of each other, i.e. f

 Byb-k

hch

 1 (K - integer values 50

55

 To not).

The pulse selector can be applied directly to the processing of analog signals (without ADC). In this case, the selector circuitry is simplified. In addition to the exclusion of their A / D converter circuit 1 with corresponding connections, the delay unit 6 and the timer 7 are significantly simplified.

Increasing the accuracy of the elimination is achieved by reducing the distortion of the pulse shape compared with the known device, as well as by

clock frequency f

tch

Once

the number of counted pulses N

will correspond to C (N Comparator 19, making a comparison With f-ry-H N, generates a code equality signal, according to which the single vibrator 22 will form a short pulse of setting the counter 17 into the zero state and the trigger one state 15. The state trigger 15, which corresponds to the switching of contacts I-III of switches 2 and 5, will remain unchanged until the arrival of a new start pulse. Counter 17 will continuously continue counting and pulse f ;.

The 5 D ° Formed one-shot 22 pulse is also clocking for counter 18, which counts the number of count cycles of Counter 17, each of which

20 duration is 1. The comparator 20 marks the point in time when the number of cycles counted by the counter 18 becomes equal to the given one (n − 1). Comparator code match signal

25-20 will translate the trigger 18 into one state, which will lead to the closure of the contacts of the key 4. The cycle of the timer 7 ends.

Introduction to device-hollow,

30 of the digital converter 1 is dictated by the need to process signals with a different follow-up period, which in turn requires the use of block 6 of delay c. variable delay time, which for analog signals is a rather complicated task, while the digitized signal can be delayed by

0 any time

To ensure synchronization, the work of the timer 7 and block 6, the frequency of the pulses on the bus 9 (f / b) clock pulses on the bus 13 (f-rtf) must

 be multiples of each other, i.e. f

 Byb-k

hch

 1 (K - integer values

five

 To not).

The pulse selector can be applied directly to the processing of analog signals (without ADC). In this case, the selector circuitry is simplified. In addition to the exclusion of their A / D converter circuit 1 with corresponding connections, the delay unit 6 and the timer 7 are significantly simplified.

Increasing the accuracy of the elimination is achieved by reducing the distortion of the pulse shape compared with the known device, as well as by

providing the possibility of choosing the optimal number of compared pulse sequences.

Claims (2)

1. A pulse selector comprising a delay unit and a key, the output of which is connected to the output bus, characterized in that, in order to improve the selection accuracy by reducing distortion of the pulse format, a minimum value selection unit, a timer, first and second switches, introduced to it, the first output of the first switch is connected to the first input of the second switch, the second input of which is connected to the key input and to the output of the smallest value selection unit, the first input of which is connected to the second output of the first switch, and the second input - with the output of the delay block, the first input coupled to an output of the second switch, a first input connected to the bus timer start, the second input - to a bus set the number of pulse sequences, the third the input is connected to the clock bus, the first timer output is connected to the control inputs of the first and second switches, and the first and second output is connected to the key control input, with This input of the first switch is connected to the input bus. 2. The selector according to claim 1, characterized in that, in order to expand the frequency range, therein An analog-to-digital converter is introduced, and the delay unit is made with variable delay time, the input of the analog-digital converter is connected to the input bus, and the output is connected to the input of the first switch, the second input of the delay unit is connected to the bus of the delay time setting, and to the fourth timer input, and the third input is connected to the bus  sampling pulses and trigger input: analog-to-digital converter.  2 ( 2 A7b In AB L Ztf 25 x Fav. H