SU1591007A1

SU1591007A1 - Device for computing exponent of exponential function

Info

Publication number: SU1591007A1
Application number: SU884453477A
Authority: SU
Inventors: Georgij L Baranov; Vladimir L Baranov
Original assignee: Inst Elektrodinamiki; Inst Modelirovaniya V Energeti
Priority date: 1988-07-01
Filing date: 1988-07-01
Publication date: 1990-09-07

Description

The invention relates to automation and computing and can be used to monitor and control processes of different physical nature, which are described by an exponential function. The purpose of the invention is to expand the functionality by calculating the value of the exponential process indicator, reaching a given level in the required time. This goal is achieved by the fact that the device for calculating the exponential function index contains a converter 1 analogue - pulse duration, triggers 2 and 3. switch 4, shift registers 5-7, adder 8, subtractor 9, reversible counter

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10, the counter 11, the output 12 of the result, the elements AND 13-18, the elements OR 19-21, the control unit 22, the information input 23. The control unit 22 comprises a pulse generator, a pulse distributor, a switch. element OR, generator of single impulses, trigger, keys, delay element, element NOT, element OR, input of the initial code, input of the operation mode, input of the initial installation, outputs. The device calculates the exponential function, changing the value from one given value to another for a specified time. 3 il.

The invention relates to automation and computing and can be used to monitor and control processes of different physical nature. which are described by an exponential function.

The aim of the invention is to expand the functionality by calculating the exponential process indicator, reaching a given level for the required time.

FIG. 1 shows a block diagram of a device for calculating an exponential function index; in fig. 2 block diagram of the control unit; in fig. 3 - time diagram of the exponential process.

A device for calculating the exponential function index contains a converter 1 analogue - the pulse duration. triggers 2 and 3, switch 4, shift registers 5-7, adder 8, subtractor 9, reversible counter 10, counter 11, output 12 of the result, AND 13-18 elements, OR elements 19-21, control block 22 and information input 23 .

The control unit 22 comprises a pulse generator 24, a pulse distributor 25, a switch 26, an OR element 27, a single pulse generator 28, a trigger 29, keys 30 and 31, a delay element 32, NOT elements 33 and OR 34, inputs for the start code 35, tasks operation mode 36 and initial setting 37 and outputs 3846.

The device works as follows. *

In the initial state, the key 30 of the control unit 22 connects the output of the generator 28 single pulses to a single input of the trigger 29. On the switch 26 of the control unit 22 (made in the form of an electronic switch controlled by the input 35 of the initial code, or as a key switch) set the initial binary code 2 ".- K, where η is the number of digits of the first and second shift registers; K is a constant calculated from the expression

^{k =} ' ^{, n} S'sh) · <”

where CS is the specified voltage level (fig.Z);

1> t - the steady-state value of the increasing exponential function

and = and _t (1-e- ⁰ *), (2)

where a is an exponential index.

The generator 24 pulses of the control unit 22 generates a sequence of clock pulses of frequency ί. of which 2p-bit dispenser 25 pulses form 2p sequences of frequency pulses ί / 2η. shifted relative to each other at time 1 / ί. the switch 26 in the unit bits of a given binary code 2 "- K connects the output of the corresponding discharge of the distributor 25 pulses to one of the inputs of the OR element 27. After installing the switch 26, the output of the OR element 27 forms a 2-digit serial binary code of the value 2 ^P - K. · Η is represented by high-order digits, and the fractional part is η by low-order digits.

The device is reset to the initial state by a signal at the control input 37 of the control unit 22. A single signal from the output of the element HE 33 is fed through the key 31 to the control input of the generator 28 single pulses, which separates a single pulse from the 2n-th output sequence of the distributor 25 pulses delayed by the delay element 32 for the duration of the clock pulse. A single impulse arrives through the key 30 at its first output and sets the trigger 29 into the single state in which it. is 2η cycles to the next pulse of the sequence 2n-th output of the distributor 25 pulses, setting the trigger 29 in the zero state. In addition, single

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the impulse from the generator 28 single impulses of the control unit 22 goes through the key 30 to the installation inputs of the reversible counter 10 and counter 11, setting them to the zero state, and also through the OR elements 20 and 21 to the zero inputs of the flip-flops 2 and 3, setting them to zero state.

A single signal with a duration of 2 steps, arriving from the direct output of the trigger 29 of the control unit 22 to the control inputs of the shift registers 5 and 7, ensures the entry of the initial binary codes into them. The registers 5 and 6 of the shift, each containing η bits each, under the action of the clock pulses of the generator 24 pulses of the control unit 22, write a single binary code, since the installation and control inputs of the shift register 5 have a single signal from the direct output of the trigger 29 control unit 22. In the shift register 7, containing 2p bits, under the action of the clock pulses of the generator 24 pulses of the control unit 22 is recorded 2n-bit initial binary code 2 ⁿ -K, coming from the output of the OR element 27 of the control unit 22 to the setup input of the register

7 shift. After writing, a single binary code is stored dynamically by circulating through the registers. 5 and 6 of the shift and subtractor 9 under the action of the clock pulses of the generator 24 pulses of the control unit 22. Element And 16 in the initial state is closed by the zero signal from the direct output of the trigger 2. The initial binary code 2 ^P - K is memorized by circulation through the shift register 7 and the adder

8 under the action of the clock pulses of the generator 24 pulses of the control unit 22. Element And 17 in the initial state is closed with zero signals acting through the element OR 19 on the direct outputs of the triggers 2 and 3.

After writing the start code to the shift register 7 on the switch 26 of the control unit 22, the binary code of time T is set, during which the exponential process (2) must reach the specified voltage level and _c (Fig. 3). After the switch 26 is installed, the output binary of the OR unit 27 of the control unit 22 generates a sequential binary code of a predetermined time T operating with a period of 2η /.

In the mode of calculating the exponential function indicator, the key 30 of the control unit 22 is closed to the generator output 28 single pulses of the control unit 22 with the converter 1 start input analogue - the pulse duration and with the single trigger input 2. The device is started by supplying a single signal from the output of the HE element 33 through the key 31 to the control input of the generator 28 single pulses of the control unit 22, which produces a pulse starting converter 1 analog - the duration of the pulse and the installation of the trigger 2 in the unit toe Converter 1 analog pulse duration after start generates a pulse signal at the output, the duration of which is proportional to the analog signal acting on the information input 23 of the device. The pulse signal of the transducer 1 analogue pulse duration opens the element And 13, the output of which is formed a packet of pulses of the first discharge of the distributor 25 pulses of the control unit 22. The number of pulses in a packet is proportional to the analog signal acting on the information input 23 of the device. This stack of pulses from the output of the element And 13 is fed to the subtractive input of the reversible counter 10, to the summing input of which, with a phase shift, the loan signals from the ηth digit of the subtractor 9 are received through the element 18 and are generated as follows. After the trigger 2 is set to the unit state, an element 16 is opened. Through it, under the action of clock pulses, a p-bit unit code from the output of the shift register 5 is fed to the subtracting input of the subtractor 9. At the same time, under the action of clock pulses, the unit code from the shift register 5 is rewritten into the shift register 6, from the output of which a 2n-bit unit code is input to the input of the decremented subtractor 9. After 2η clock cycles, a consecutive binary result code is formed at the output of the difference between the subtractor 9, the η least significant digits of which contain zeros, and the η most significant ones - ones. The low η digits are written under the action of clock pulses through the shift register 5 to the shift register 6, and the high ones - to the shift register 5. In the process of rewriting the lower η bits of the result from the shift register 5 to the shift register 6, the element AND 16 is blocked by a zero signal at the output of the OR element 34 of the control unit 22, since a single signal at the output of the element OR 34 acts only during the formation of pulses in the first η bits dispenser 25 pulses.

In the following 2p cycles when subtracting

unit code η most significant bits shifted under the action of clock pulses

from shift register 5, from zero code η

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younger bits, shifted under the action of clock pulses from shift register 6, the loan output from the subtractor 9 generates a loan signal from the ηth digit, which through the element 18 arrives at the summing input of the reversing counter 10 during the pulse at the ηth output p ' distributor 25 pulses of control unit 22. Since the loan signals from the nth digit at the output of the subtractor 9 are not formed in each subtraction cycle containing 2p cycles, and the batch pulses at the output of the And 18 element act with a frequency of ί / 2η, an additional code of the difference between the number is accumulated in the reversible counter 10 pulses in a pack and the number of loans from the η-th digit at the output of the subtractor 9.

After starting the device, a single signal of the trigger 2 opens the element OR 19 through the element OR 19. The switch 4 at a zero signal at the direct output of the trigger 3 allows the sequence of pulses of the first discharge of the distributor 25 pulses to pass through the element 17 to the input of the adder 8. Every 2n clock cycles sequential Binary code, shifted, starting with the low-order digit, under the action of clock pulses e of the output of the shift register 7, is increased by one of the least significant digit and is again recorded in shift register 7.

In the future, the device operates similarly until then. until at the output of the converter 1 analogue - the pulse duration does not establish a zero signal. In this case, the element And 13 is closed and the flow of the pulse packet to the subtractive input of the reversible counter 10 is terminated. The summing input of the reversing counter 10 still receives loan signals from the ηth digit from the output of subtractor 9 until then. until the reversible counter 10 overflows. This will happen when the number of loan pulses received at the summing input of the reversing counter 10. reaches the number of pulses in the batch received at the subtracting input of the reversing counter 10. The overflow signal of the reversing counter 10 sets the trigger 3 to one state and through the element OR 20 resets the trigger 2 to zero state. The zero signal of the direct output of the trigger 2 blocks the element AND 16, stopping the subtraction process in the subtractor 9. The signal from the direct output of the trigger 3, which is in the unit state, switches the switch 4 so that the output of the element OR 27 of the control unit 22 is connected through the element AND 17

with the input of the adder 8. Every 2p cycles

serial binary code specified

time T, acting at the output of the element OR 27 of the control unit 22, is summed by the adder 8 with the binary code shifted under the action of clock pulses from the output of the shift register 7! The result of the summation under the action of clock * pulses is again recorded, starting with

10 low order, in register 7 shift. At the same time, every 2p clock cycles to the information input of the counter 11 through the element 14, opened by a single signal of the direct output of the trigger 3, a pulse is received in sequence 15 of the first output of the distributor 25 pulses of the control unit 22. Therefore, in the counter 11 the number of cycles of summation of the binary code of a given time is calculated.

20 T. The device operates in this way until the transfer signal from the 2nth digit appears at the output of the adder 8. This transfer signal is separated by an AND 15 element, the output pulse of which through the element

25 OR 21 sets trigger 3 to zero. The zero signal of the direct output of the trigger 3 blocks the element And 14, and the score in. counter 11 is terminated. From the zero signals of the direct outputs of the flip-flops 2 and 3 on

30 output element'IL or 19 formed a zero signal, which closes the element And 17, stopping the summation process in the adder 8. In the counter 11, an indicator of the exponential process is formed.

35 which, within the required time T, reaches a predetermined voltage level 1) _s (FIG. 3). The value from counter 11 goes to output 12 of the result.

The algorithm of the device based.

40 is given on the following ratios. For the exponential process (2) the expressions are

. and (and) = ish (1 ~ e ^-0th '). (3)

₄₅ and 02) -and _t (1 - _e - “ ¹² ). (four)

If we denote and (and) = and, and (1d) = I. then

instead of (3) and (4) have

_e -O2 ₌ , _1k (6)

looking for

Dividing (5) by (6) and logarithming the resulting expression, get

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^aT = H ¹ 'k) -CH ¹ - ^) - < ⁷ >

where T = X2-P.

In view of (1), expression (7) takes

view

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'Φ'Ή) · < ⁸ >

Since, in the initial state, an additional code of the value K equal to 2 ^P ? K is written into the shift register 7, the transfer from the 2d digit of the adder 8 occurs after accumulating the value (8) in register 7. Consider the algorithm for the formation of the second number in the right-side of the expression (8). Denote

'= - "*" · ST

'and

where x = 1 - -.

From (9) you can write

x = e ~ ^y . (ten)

Differentiating (10), have

bh = bu = - x bu. (eleven)

Replace differentials in (11) increments

Δχ = X! - Χί- ι = - χι- 1 Doo. (12)

Take the weight of the increment DN = 2 ' ^p , where η is the width of the registers 5 and 6 shift. Then (12) can be written as

Χί = hm - hm -2? (13)

The algorithm (13) of the initial conditions xo = 1 is implemented by the subtractor 9, the shift registers 5 and 6 and the element 16.

Increments Δy with a weight of 2 ' ^p in the form of a stream of pulses of the first discharge of the distributor 25 pulses arrive through the switch 4 and the element 17 to the input of the adder 8, which together with the shift register 7 forms the value

( ₁ - ^) = ΣΔν · (AND)

The summation of the increments Duv (14) ends when the argument x reaches the value

x = 1-7T- · 05)

• it

The overflow signal of the reversible counter 10 is generated when the argument x reaches the value (15). Indeed, the arrival of a burst of pulses, the number

and

which is proportional to the size, with Th

the output element And 13 on the subtracting input of the reversible counter 10 forms in it

the value of 1 - -γ—, if we accept that the maximum

The maximum capacity of the reversing counter 10 is 1.

On the other hand, the summing input of the reversible counter 10 receives a stream of increments of the argument Δχ with a weight of 2 ' ⁿ in the form of loan pulses from the ηth digit of the subtractor 9. After the end of the action

the bursts of pulses at the subtracting input of the reversible counter 10, the flow of increments Δχ at its summing input leads to the overflow of the reversible counter 10 at the moment of the fulfillment of the relation (15). We note that the proportionality coefficient 1 / Fs when forming the value

I - -Y- in the reversible counter 10 takes into account

is made by selecting the parameters of the converter 1 analogue - the pulse duration.

Thus, for the time after the device starts up until the reversing counter 10 overflows, the initial binary code 2 ^П - К shift register 7 adds the value у = - € п (1 - Ч / Чт). Then during the time after the overflow of the reversible counter 10 to the overflow of the shift register 7, when the relation (8) is fulfilled, in the counter

II is formed by the value of the exponent a of the exponential process, which is on the voltage level. H reaches a predetermined voltage level of CH in the required time T. Indeed, if relation (8) is satisfied, then in register 7, the shift has

2 "-K + § Т-йт / 1 - - \ = 2 ^П ,

1 \ Shch /.

The integer part of the number is represented in the η most significant bits of the shift register 7, and the fractional part of the number is represented in the lower order digits.

Claims

Claim

A device for calculating the exponential function indicator, which contains an analogue converter - pulse duration, first and second triggers, switch, first, second and third shift registers, adder, subtractor, counter, first - sixth elements I. first, second and third elements OR and block control, containing a pulse generator, pulse distributor, switch, the first and second elements OR. the delay element, the NOT element, the first and second keys, the output of the pulse generator is connected to the input of the pulse distributor and the synchronization inputs of the first, second and third shift registers, 2p outputs of the pulse distributor (where η is the number of digits of the first and second shift registers, 2n is the number of digits the third shift register) is connected to the corresponding information inputs of the switch of the control unit, the control input of which is connected to the input of the initial device code, 2 n outputs of the switch of the control unit phenomena connected to the corresponding inputs of the first element OR block

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control, the first output of the pulse distributor of the control unit is connected to the first inputs of the first and second elements And, the 2nth output of the pulse distributor is connected to the input of the delay element of the control unit and the first input of the third element And, the second input of which is connected to the transfer output of the adder, the first output of the first key is connected to the installation input of the counter, the control input of the first key is connected to the input of the operation mode setting of the device, the control input of the second key is connected to the input of the initial installation of the device va, the information input of the second key is connected to the output of the NOT element of the control unit, the input of which is connected to the logical zero input of the device, the information input of the device is connected to the information input of the converter analogue pulse duration, the output of which is connected to the second input of the first element And, the direct output of the first trigger is connected with the first input of the fourth element And, the direct output of the second trigger is connected to the control input of the device switch and the second input of the second element And, the output of which is connected with the information input of the counter, the output of which is connected to the output of the device result, the output of the subtracter difference is connected to the information input of the first shift register, the output of the first element OR is connected to the first input of the fifth element AND, the output of which is connected to the first input of the adder, the output of the sum of which is connected to the information the input of the third shift register, characterized in that, in order to extend the functionality by calculating the exponential process indicator, reaching a given level for the required time, a reversible counter is entered into it, and a single pulse generator and a trigger are entered into the control unit, the zero setting inputs and whose units are connected respectively to the 2 nth output of the pulse distributor and the first output of the first key, whose information input is connected to the output of a single pulse generator whose control and clock inputs are connected respectively with the output of the second key and the output of the delay element

control unit, ίth (I = 1.2 ..... n) the output of the pulse distributor is connected to the ΐth input of the second element OR control unit, and the output of the first element I is connected to the subtractive input of the reversible counter, the summing input of which is connected with the output of the sixth element AND, the output of the overflow of the reversible counter is connected to the first input of the second element OR and the installation input of the unit of the second trigger, the input of the zero setting of which is connected to the output of the third OR element, the second output of the first key of the control unit is connected to the input of the zap the converter's analogue clip is the pulse duration and the installation input of the unit of the first trigger, the zero setting input of which is connected to the output of the second OR element, the first output of the first key of the control unit is connected to the installation input of the reversing counter, the second input of the second OR element and the first input of the third OR element, the second the input of which is connected to the output of the third element And, the output of the first shift register is connected to the second input of the fourth element And and the information input of the second shift register, the output of which go connected to the input of the decremented subtractor, the input of which is subtracted is connected to the output of the fourth element And, the direct output of the control unit trigger is connected to the installation and control inputs of the first shift register and the control input of the third shift register, the output of which is connected to the second input of the adder, the output of the first element OR the control unit is connected to the setup input of the third shift register and the first information input of the device switch, the output and the second information input of which is connected respectively It is clear that the second input of the fifth element And the first output of the pulse distributor of the control unit, the direct outputs of the first and second triggers are connected respectively to the first and second inputs of the first OR element, the loan output of the subtractor is connected to the first input of the sixth element And, the second input is connected to η- m output distributor pulses of the control unit, the output of the second element OR the control unit is connected to the third input of the fourth element I.

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