SU1589293A1 - One-digit analog adder - Google Patents

Abstract

The invention relates to computing, for example, to discharge-to-analog adders and can be used as a base unit for synthesizing mathyric multipliers, functional converters, and other analog-to-discharge devices. The aim of the invention is to extend the functionality of discharge-to-analog adders by multiplying the input values by fractional scaling factors, which is achieved by introducing analog-to-bit converters and organizations, both transfers from the lower bits to the older ones, and loans from the older bits to the younger ones. . The device contains N analog adders 1 (where N is the number of bits), N analog-bit converters 2, M (where M is the number of terms) of the input N-bit buses 3 and 4, input 5 of the lower-order transfer, input 6 high-order loans, bus 7 positive reference voltage, output N-bit bus 8, output 9 of the low-order loan, output 10 of the high-order transfer. An analog-to-bit converter contains an analog inverter 11, two analog-to-digital converters, two digital-to-analog converters, two differential amplifiers. 2 Il.

Description

  . one

(21) 4486809 / 24-24

(22) 20.06.88

(46) 08/30/90. Bul No. 32 (70 Institute for Modeling Problems in the Power Engineering of the Academy of Sciences of the Ukrainian SSR and the Special Design and Technological Bureau of Modeling Tools with Experimental Production of the Institute for Modeling Problems in the Power Engineering of the Academy of Sciences of the Ukrainian SSR (72) V.P.Romantsov, S.Ya.Gilgurt, A.F. Novitsky and L.P. Dobrydin (53) 681.335 (088.8) (56) Copyright Certificate of the USSR 423132, class G 06 G 7/14, 1971.; Author's certificate of the USSR No. 423133, class G 06 G 7/14, 1971.

(54) SINGLE-ANALOG SUMMATOR (57) The invention relates to computing, for example, to discharge-analog accumulators and can be used as a base unit for the synthesis of matrix multipliers, functional converters and other discharge-analog devices. The aim of the invention is to extend the functionality of analog-to-analog adders by multiplying the input values by fractional scaling factors, which is achieved by introducing analog-to-bit converters and arranging them as hyphens.

(L

L. /

Loans, and loans of the most senior bits in the young. The device contains n analog adders 1 (where n is the number of bits), n chalog-bit converters 2, ha (where m is the number of terms) of the input n bit buses -3 and 4, input 5 of the transfer of the low-power bit , input 6 of the higher-order loan, bus 7 polo Invention relates to computing, in particular to hybrid computing, and can be used as a basic unit for the synthesis of matrix multipliers, functional converters and other analog-to-analog devices,

The purpose of the invention is to expand the functionality of the device by multiplying the input values by fractional scaling factors,

Figure 1 is a diagram of the discharge of a bottom-to-analog adder for a particular case where the number of bits

p 3, the number of components and 2; Fig. 2 shows an embodiment of an analog-bit converter.

Analog-to-analog adder (fig, 1) contains ana-colder summatorosis 1.1, 1.2, 1.3 s (t + 2) inputs, n analog-to-bit converters 2.1, 2.2, 2.3 ,. hectares of input p-razdny tires 3.1, 3.2, 3.3, 4.1, 4.2, 4.3, input 5 for transferring the low-order bit, input 6 for the high-order loan, bus 7 for the positive reference voltage, output n-bit for the bus 8, exit 9 of the low-end loan, exit 10 of the transfer of the older bit, yes.

An analog-to-bit converter (Fig. 2) contains an analog inverter 11, two analog-to-1 (n-12, 12.2 converters, two digital-to-analog converters 13.1, 13.2, two differential amplifiers 14.1 and 14.2,

The size of the analog-digital and analog-to-digital converters depends on the number of systems used in the following way.

L,

a positive reference voltage, an output n-bit bus 8, a dead-end output 9, a higher-order transfer output 10, the Anap-bit converter contains an analog inverter, two analog-to-digital converters, two digital-to-analog converters, two amplifiers

differential signal, 2 Il.

where L is the size of the converters K is the base of the number system;

 operator of the nearest integer greater than or equal to the original value.

The device works as follows.

When the device operates in a number system with a base equal to ten, the width L of the converters included in the analog-bit converters 2 is four. For convenience of describing the operation of the device, assume that the unit of the input signal corresponds to a voltage of 1V.

Then the voltage value П ,, supplied to the bus 7 of the positive reference voltage of the device, must be equal to 10V.

Analog-to-analog adder performs an operation of the form:

Have

(one)

Imagine (1) in bit form

  P

where y, x ,, x, are bit vectors generated by the following sample.

Y, x, i: K - x ;,

; . . ., p ,, (30

H

i-

where K is the base of the number system

Consider the example, when, n 3, g, 3/4, g 1/4, X, 268, hg 485. Then, in accordance with O), the result of the operation should be

  2 .. 268 -I- -t-

 four

 322.25.

The device operates according to the following algorithm:

a) the operation of rounding M is the final allocation of the fractional part in each bit, multiplying it by the value of K 10 and transmitting the result

to the next least significant bit;

b) the transfer operation P is similar to the usual transfer in digital adders.

In this way, we have the result: 3

210

10 3

at 2-10

.ten

322.

If necessary, the fractional part of the low bit can be saved and used as an additional analog bit. Its value lies in a continuous segment (O, ..., K).

The resistance values of the resistors in the input branches of analog adders 1 leading to the input buses 3 and 4 are chosen inversely proportional to the scale factors by which the variables X are multiplied, and Xj. In this example, they are equal to R / 9 respectively. 4R / 3 and R / 92. 4R. The resistance value of the resistors in the feedback circuits of the adders G is chosen inversely proportional to the base of the K number system (R / IO).

The resistance value of the resistors in the input (t + 1) - X and (t + 2) -x branches of the analog adders 1 leading to the outputs of the analog-bit converters 2 is chosen to be single.

Then Ki) (

 2 (; - l

where and

and

2Ci + i)

),

(five)

five

0

and

Ui)

ъ ()

(eleven

(g

and

i (iHV

, 0) 2 (140

voltage at the output of the analog adder

eleven;

the voltage at the i-th discharge of the input p-discharge of the bus 31; voltage at the i-th discharge of the input p-discharge of the bus 41; the voltage at the third output (i-l) -ro of the analog-bit converter Y-);

the voltage at the first output (i + l) -ro of the analog-to-bit converter.

25

From (5) it follows

uui) -0.1 C-rU, ()) C (O + U (-, + and (, H,)).

(6)

At the initial moment of time, input signals are supplied to the p-bit buses 3 and 4, namely: input 3.1 is voltage 2B; input 3.2 volts 6 V; at input 3.3 - voltage, 8 V; at input 4.1 - voltage 4 V; on input 4.2 - direct burned 8 V; input 4.3 - voltage 5V.

At the outputs of analog adders, voltages appear:

  -0.1 (-f- 2 + -0.25 V;

U (U) -o.I- | -b + -f

-h

+ 0 + 0)

+ c + 0) -0.65 V; 3

) -o, 1 (-

+ 0 + 0) -0.725 V.

one

four

8 + -7- 5 +

These voltages are applied to the inputs of analog-bit converters 2,

Let us consider in detail the work of analog-bit converters on the example of the second bit. Voltage and -0.65 V are inverted by analog inverter 11 into voltage:

U) 0.65 V,

which is converted by an analog-to-digital converter 12.1 to code 0000 (2). This code is fed to a analogue analog converter 13.1 and is converted to voltage Uj, ". A B. This voltage of the differential signal capacitor 14.1 is subtracted from the output voltage of the inverter CC and the result is multiplied by the coefficient K:

and

Have

K (UU- ui, o „,)

 10 (0.65-0) 6.5 V.

(eight)

This voltage is converted by an analog-to-digital converter 12.2 to code 0110 (2), which is fed to a digital-to-analog converter 13.2 and converted to a voltage Uugi, 2 bV. At the output of the difference signal amplifier 14.2, the voltage becomes

 K (Uy, - scapg) 10 (6.5-6) 5 V.

(9)

Thus, the analog-bit converter 2.1 converts the analog voltage and (, 1 -0.65 V into three discharge voltages:

4an, ltl S;

(d) itzap gsg) 6BJ

 and

ha.)

 5B,

Substituting (8) into (9), we obtain

Kits K - Ui q + Kitsd „2+ c

Using (7) and (6) dl, we arrive at the following relation:

44T 8 + 4 4 (2) 84 +%.) 2)

-ki, „„, + 10 + ufi., + 0,1 ujj,),

(11) 50

According to (ii) the sum of the input values of the analog adder K2 is

fits on the whole part of the syb-L) lH)

part and

2 (4)

and velushna and

2 (2)

Ha

The scaling excess of the base of the number system. These values are the output voltage of a given discharge, the borrowing voltage, and the transfer voltage, respectively.

Analogous r-razdnye drives 2.1 and 2.3 operate in a similar way. Voltages appear at their outputs.

and

W 2 (iy

op; .-2B; and D, 5B;

, OB; ujf ,, 7В; U2% 2.5 V.

Loan voltage Ujfil 5 B is fed to (ha + 2) -th input of the analog adder 1,2, the voltage of the loan)

 5V is fed to the (in + 2) -ft input of the analog adder 1.3. As a result, voltages appear at the outputs of these adders.

) -0.1 (- | -.6 4 - .. 8 + 5 +

thirty

+ 0) -1.15 V;

. T

5 + 5 + 0)

 -1,225 V.

These voltages are converted by analog-bit converters 2.2 35 and 2.3 to the following signals:

and

(O 2 (r1

(O 2 (3)

1B | and (L

(3)

1B; Ujtj)

0

1B; 2B; U. ,,,, (),

5B; 2.5V.

The transfer voltage U2 (2) 1 V is fed to the (t + 1) -th input of the analog adder 1.1, the transfer voltage

2 (9) is fed to the (t +) - th input of the analog adder 1.2. As a result, voltages appear at the outputs of these adders:

-o, K-J-0, 35 V,

2 -1- 4

4 + O +

-0,1 (- | -.6 +, + 5 + 1)

- -1.25 V

These voltages are converted by analog-bit converters 2.1 and 2.2 to the following signals:

S; U,

and

(3)

AT; and

(g)

2 (2)

2 (1)

(

2B; and,(

 5 V

5 V

This concludes the operation of the device. At the outputs of the device there are voltages:

, (2)

ZV ;. and;, 2B; and, (,, 2В;

one

which corresponds to the bit representation of the number 322. An analog residue of 2.5 V is present on

output and can be used to improve the accuracy of calculations.

Claims (1)

Invention Formula Analog-to-analog adder containing p (where p 1,2, ...) analog adders with (t + 2) inputs (where ha 1,2, ...), hectares of which are connected respectively to the hectare input n -disable tires, about t i and - h and s. and with the fact that, in order to expand the functionality by multiplying the input values by fractional scaling factors, n analog-bit converters were introduced into it, of which consists of an analog inverter, the first and second analog-to-digital converters, the first and second digital-to-inverter converters leu and the first and second difference signal amplifiers, the outputs of the analog adders are connected to the information inputs of the corresponding analog-bit converters, the first outputs ix (where i 2,3 / .. n) of the analog-bit converters are connected to (t + 1) -m inputs (il) -x analog adders, second outputs n analog-bit converters form the output n-bit bus, the third outputs jx (where j 1,2, ... n-1) analog-bit d10 15 AO 8929310 The transducers are connected to (t + 2) -th inputs (j + 1) -x analog adders, the first output of the first analog-bit converter and the third output of the n-th analog-bit converter are respectively the transfer output of the higher bit Yes, and the output of the lower-order borrowing of the device, (that 2) -th input of the first analog adder and (t +) - th input of the n-th analog adder are respectively the input of the higher-order borrowing and the input of the transfer of the lower-order device, inputs the reference voltage of all analog-bit transformers The drivers are connected to the bus of the positive reference voltage of the device, the information input of each analog-to-converter converter through the series-connected analog inverter., the first analog-to-digital converter and the first digital-analog converter are connected to the first output of the analog-to-bit converter and the first the input of the first amplifier of the diverse signal, the second input of which is connected to the OQ formation input of the first analog-digital converter, the input voltage of which connected to the input of the reference voltage analogue of the bit converter and the input of the reference voltage of the first and second digital-to-analog converters and the second analog-to-digital converter, whose information input is connected to the output of the first differential amplifier, and the output is connected to the second output of the differential signal bit converter and the first input of the second differential amplifier, the output of which is the third output of the analog-bit converter Ate, and the second input is connected to the output of the first differential signal amplifier. 35 40 45 FIG. 2