SU1280400A1 - Analog-digital multiplying device - Google Patents

Abstract

The invention relates to analog computing and can be used in automation systems and devices. Purpose and bret- NIN is an increase in multiplication accuracy. The goal is achieved by changing the form of representation of the discrete part of one of the factors instead of the directly signed code used in the known device, shifted with the binary code, which eliminated the sources of errors associated with providing four-quadrant operating mode - inverters and analog switches from signal circuits Y; triplets. The main structural differences consist in introducing into the device the first, second, and third sources of the reference voltage and the control unit for multiplying by logic (A zero, containing two elements SH-NOT and NO-NO, as well as available connections between elements and blocks, and this ensures the achievement of the goal. 1 Il.

Description

The invention relates to analog computing and can be used in devices and automation systems.

The purpose of the invention is to increase the accuracy of multiplication.

The drawing shows the scheme of analog-digital duplicating device .v.

The multiplying device contains an analog-to-digital converter (ADC) 1, first 2, second 3 and third 4 reference voltage sources (ionj digital-analogue converter (DAC) 5, multiplying digital-analogue converter (UTsAP) 6, analog multiplier (LP) 7, adder 8, summation unit - subtraction (BSV) 9, control unit (WU) 10 by multiplication, by logical zero, inverter 11, switch 12, first 13 and second 14 inputs and output 15, devices. In addition, BU 10 contains the elements OR NOT 16 and 17 and the element AND NOT 18. The listed elements and blocks are connected by link This schema.

Analog-digital copying device works as follows.

The first alternating factor X comes from the input 13 of the device to the information input of the ADC 1. The reference inputs of the ADC 1 are attached to the reference voltages of the E-E ION

2 and 3:

N

k-2 -2 ..

() where X. - the maximum value of the multiplier X; S is the number of ADC bits 1. The result of the analog-to-digital conversion is represented by a parallel shifted binary code n: (x + 2 d + k), o. where d | 5-g, -d quantization interval; whether. - quantization error, reduced to the input of the ADC 1, the code signal n is fed to the corresponding bit inputs of the D / A converter 5, in which the code n is converted into analogue form, where the main output of the D / A converter 5 forms at the complementary output - its complement to the maximum signal

X j corresponding to the input code value -1. In this way:

ohp

() d.

. “Oka tsag

d-x-d). (four)

The signals xj and go respectively to the inverting and non-inverting inputs of block 9, to the two other non-inverting inputs of which a factor X and a bias voltage E of source 4 are applied. At the output of block 9, a residue is formed

(x + xj). (5)

Substituting expressions (3) and (4) into the last relation and transforming, we get

 X k (,. (6) Putting, we get

(7)

,

5 where K is the scale factor of the summation - subtraction result, the value of which (to maximally reduce the effect of the error 0 AP 7) is chosen close to the value of the number of quantization levels of the ADC 1. Continuing on one of the inputs of the AP 7, the remainder x multiplies Y, which is fed from the input 14 of the device.

Claims (1)

The result of the multiplication is r ,, (a). The scale factor AP 7. At the same time, the discrete part of the multiplier X in the form of a binary shifted code n is fed to the corresponding bit inputs of UCAP 6, with N-1 lower bits of the code n fed to UCAP 6 directly 10. The logical signal at the output of the element OR-NOT 17 BU 10, which controls the high-order bit of UCAP 6, is zero for P42 and one for n2. Accordingly, the signal at the output of UCAP 6 is determined by the ratio (dt-l) Y, GK (% DAC 4 To eliminate the bias component, the resulting digital-analogue multiply, an additional input circuit is used: inverter 11 - key 12 The control input of the latter is connected to the output of the element NOT BU 10, on which a logical signal equal to zero is formed, and if the unit is used in all other cases. The signal at the output of the switch 12 ./JY M o, the results of analogue Z and discrete analogue analogue Zj, as well as the compensating signal Z, are fed to the inputs of adder 8 with summation coefficients of 1 / K; 1 and cd respectively. The output of adder B is the result of multiplying Z: Z IZ + Z, + K z, -K & Y + К d 1 dor к (К -К) Y + ii- u J, (J ца п-. Note that the value corresponds to the values of the factor X and the result Z, equal to zero. Therefore (K „2 -K) Y + ( - | - -Kan xY. (12 Equalize to the scale factors of multiplication of the discrete and analog parts of K an and putting Kddp K-, we will finally get it. (13) Invention Analog-to-digital multiplying device containing an analog-to-digital converter, digital-analogue converter, multiplying digital-to-analog converter, analog multiplier, summation-subtracting block, key, inverter and sum op, the output of which is the output of the device, and the first and second inputs are connected respectively to the multiplying digital-to-analog converter and to the output of the analog multiplier connected by one input to one of the information inputs of the device and to the analog input of the multiplying digital-analog converter, and the other input to the output of the summation-reading unit, the digital VHODYs of the lower bits of the multiplying digital-analogue i converter are connected to the corresponding bit inputs of the digital-analogue terminal The generator and the corresponding bit outputs of the analog-digital converter, whose input is another information input of the device, characterized in that, in order to improve accuracy, it contains the first, second and third sources of the reference voltage and the control unit for multiplying by a logical zero, in the form of two OR-NOT elements and an NAND element whose output is connected to the control input of the key, and two inputs are connected respectively to the output of the first and the inverting input of the second OR-NOT element, group The inputs of the first element OR of the control unit of the multiplication by a logical zero are connected to the corresponding outputs of the lower bits of the analog-to-digital converter, the high-level output of which is connected to the high-level input of the D / A converter and the inverting input of the second element OR-NOT connected non-inverting input and output, respectively, to the output of the first element OR-NOT of the control unit multiplying by a logical zero and to the digital input of the higher bit of the multiplying digital analogue a two-input analog-to-digital converter inputs to the outputs of the first and second reference voltage sources, respectively; three non-inverting inputs of the addition-subtraction unit are connected respectively to the information input of the analog-to-digital converter, which complements the output of the digital-analog converter and the output of the third reference voltage source its inverting input is connected to the main output of the digital-to-analog converter, the third input of the adder is connected via a key to the output y inverter having an input coupled to the analog input of multiplying digital to analog converter. Y ; // r /