JPS63217828A - Serial parallel type a/d converter - Google Patents

Abstract

PURPOSE:To attain cyclic serial parallel A/D conversion by adding an output of a comparator at the least significant digit in the final parallel A/D conversion to the least significant bit so as to employ a parallel A/D converter outputting a value smaller by 1LSB than the result of A/D conversion. CONSTITUTION:In the parallel A/D conversion where the low-order bit is obtained in adding a high-order bit and the low-order bit, the output of the comparator having a comparison voltage of 1/2.Vref/2N (N is the resolution of the parallel A/D converter and the comparison voltage in an example of the figure is 1/16.Vref because of N=3) among comparators constituting the parallel A/D converter, that is, Q0 is added to the least significant bit. When the input Q0 is smaller than the comparison voltage, the result is '0' and when larger, the result is '1'. Thus, in adding the value to the least significant bit, the output code is a value subject to correct A/D conversion.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an analog/digital converter (A/D converter) that converts an analog voltage into a digital value, and particularly to an analog/digital converter (A/D converter) called a series/parallel type A/D converter. Regarding A/D converters.

[Conventional technology]

For simplicity, a series-parallel A/D converter is used for the upper 3 bits and lower 3 bits, and the upper bit and lower bit are overlapped by 1 bit to obtain a 5-bit conversion result. Think in terms of conversion methods.

What is the serial/parallel A/D conversion method? In the case of a two-stage configuration, the first stage parallel A/D converter performs coarse A/D conversion to obtain the upper bits, and then the first stage performs A/D conversion from the input signal. The lower bits are obtained by subtracting the remaining amount and converting the remaining bits into A/D again using a parallel A/D converter.The upper bits and lower bits are combined to obtain a conversion result with a predetermined resolution.The upper bits and Adding 1 bit overlap when adding the lower bits means performing the second conversion within the range of 2LSB of the upper bits, which means that the first conversion error is corrected during the second conversion. Can be done.

Therefore, the first-stage A/D converter has a resolution of 1/2LS of the first-stage resolution.
Since an accuracy of B is sufficient, the accuracy required for the elements constituting the A/D converter is also moderate.

Specifically, in order to obtain a 5-bit conversion result without overlapping the upper bits and lower bits, an accuracy of ±1/2 LSB is required for the upper 3 bits.
The difference in tl becomes noticeable as the result of 5-bit conversion becomes large by overlapping the bit and the lower 3 bits by 1 bit, and the requirements for device accuracy become stricter.

Here, we will consider how to obtain the lower bits and how to add the upper bits and lower bits. When subtracting the A/D conversion result at the first stage from the input signal to find the lower bits, if we subtract the A/D conversion result at the first stage as is, we get 2.
Generates both positive and negative sign values as the input for the first stage. As a result, when adding the upper bit and lower bit with 1 bit overlap, subtraction is actually required, which complicates the hardware function. Furthermore, it is inconvenient if the input voltage is only positive or negative in an A/D converter with a single power supply. Therefore, when subtracting the first-stage A/D conversion result from the input signal, if you subtract a value less than ILsB from the first-stage A/D conversion result, the input of the second-stage A/D conversion will be positive or negative. There will only be one sign. Also, when adding the upper bit and lower bit, the upper bit is set to a value less ILSB than the original A/D conversion result.
If the /A-converted value is subtracted from the input signal and used as the second-stage input, the second-stage input will not be one sign, and there will be no need to consider subtraction when adding the upper bits and lower bits.

However, if the A/D conversion result of each stage is originally "0" and the smaller value of ILSB is used as the output code of the A/D converter, the output code will be negative and the force will be "0" or In the case of "1", the output code is #'i0.

In this way, in the series-parallel A/D conversion method, the upper bits and lower bits are added in an overlapping manner to obtain a predetermined A/D conversion method.
In the method of obtaining /D conversion results, the first-stage parallel A/D converter is an A/D converter that outputs a value less ILSB than the normal A/D conversion result, and the D/A conversion is performed accordingly. The system that also outputs both signals is excellent as a single power supply IC. This method has been proposed in Japanese Patent Application No. 59-079504.

Tsuru, -・6 When using a multi-stage configuration, use an A/D converter that outputs the conventional A/D conversion result as is for the final stage parallel A/D conversion, and use the above A/D converter for the other stages. A D converter may be used.

[Problem that the invention seeks to solve]

In the above series-parallel A/D conversion system, the parallel A/D conversions at each stage are cyclically converted into the same parallel A/D conversion system.
Consider executing it with a D converter.

Although this will slow down the conversion speed, the chip area and power consumption will be significantly smaller, and there are many advantages when considering integration with other digital signal processing circuits.

However, as a parallel A/D converter, a parallel A/D converter that outputs a value ILSB smaller than the original conversion result
When a converter is used in a cyclical manner, the A/D conversion result at the final stage also outputs a value smaller than ILSB. Therefore, in order to make a correct code, it is necessary to add "1@" to the obtained code.
All you have to do is add “.

However, as mentioned above, there are cases where the input of the parallel A/D converter is originally an input that should be converted to "1", and when it is originally an input that should be converted to "1".
In both cases, the output code is @θ'' when the input is to be changed to 'm. Therefore, if 11'' is always added to the least significant bit, the output code will be 1'' even if the input voltage is 0. Therefore, in the conventional art, it is not possible to construct a cyclic serial-parallel type A/D converter using a parallel type A/D converter that outputs a value ILSB smaller than the conversion result.

In order to avoid this, the output code of the parallel A/D converter is to output the A/D conversion result as it is, and when adding the upper and lower bits, the ILSB of the upper bit is subtracted from the upper bit. There are possible ways. However, in this method, subtraction must also be performed in the addition part, which causes the problem that the logic becomes complicated and the amount of hardware increases.

It is an object of the present invention to provide a cyclic series-parallel type A/D converter in which the above-mentioned problems are improved by making only the converter receive the comparison voltage.

[Means for solving problems]

The serial-parallel A/D converter of the present invention is a parallel A/D converter that outputs a value ILBS smaller than the result of A/D conversion as an output code, but N-bit parallel If the A/D conversion result of the N-bit parallel A/D converter is @0, the output is @0. It is a comparator that outputs 11" if the input voltage is larger than the comparison voltage, and outputs @θ" if the input voltage is smaller than the comparison voltage. Only when the output code of the parallel type A/D conversion is added, the least significant bit is the output of the comparator whose comparison voltage is the reference voltage 72N + 1 among the comparators configuring the N-bit parallel type A/D converter. It is configured such that the signals are added to obtain a digital output code.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

In the figure, the parallel A/D converter outputs the following code based on the input vtw II. However, Vrd is a reference voltage.

(n is an integer of 1d:, n46), "binary representation of n"
The output code is a value smaller than ILSB from the A/D conversion result.

The input for the second parallel A/D conversion to obtain the lower bits is ILDS from the input signal and the first A/D conversion result.
The difference between the smaller value and the D/A converted value is taken, and the difference is multiplied by 4 in order to match the input range. Therefore, input signal IVxN(1), A/D conversion result m1
When the output code is "m-1", the input V f N +21 for the second A/D conversion is as follows.

However, when m=Q, the output code is “0” and VIN is VIN (2) = 4 Vz N (1)
(b).

In order to realize the above, the switches of the capacitor array in the figure are changed as follows. The period during which the switch Sr is turned on and the input is sampled is 13'o depending on the output of each comparator as the calculation period after the switch Sr is turned off.
Switch zst to the reference voltage side or the connection side. However, if the output Qi-s of the switch 5iFi comparator is "1", it is switched to the reference voltage side, and if Qi-s is "0", it is switched to the ground side. Note that So is always switched to the reference voltage side.

The output of the comparator is Qi="1" if the input of the comparator is larger than the comparison voltage, and Qi="1" if the input of the comparator is smaller than the comparison voltage.
Output. Furthermore, equations (a) and (b) can be derived by establishing equations for conservation of charge between the input sample period and the calculation period. The lower bits are determined by A/D converting the VIN (21) obtained in this way again using a parallel A/D converter.

The obtained upper bit and lower bit are added with 1 bit overlap, but the lower bit has a value smaller than ILSB except when the input corresponds to 'mO'.

In the present invention, when adding the upper bits and lower bits,
Parallel A/D variation of `` and `` to find lower bits -12-''
' In the conversion, the comparison voltage of the comparators constituting the parallel type A/D converter is 1・Vr e j <N is parallel ヱ
This is the resolution of a 2M type A/D converter, and in the example shown in Figure 1, N = 3.
Therefore, the comparison voltage is -L -Vref) By calculating the least significant bit of the output of the comparator, that is, Qo, the output code can be correctly A/D converted and should be closed only at the final conversion. .

〔Effect of the invention〕

According to the present invention, cyclic serial-parallel A/D conversion can be performed using the least significant bit of the output of the lowest comparator in the final parallel A/D conversion. Also A
Compared to the case of using a parallel type A/D converter that outputs the /D conversion result as it is, there is no need to perform subtraction in the addition section, and the logic can be simplified and the amount of hardware can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. Qo~Qt・River...Comparator, Co~C7, Cf・
...Capacitor, So~Sy, Sr...
switch. Vr = 1st evening 07F Ot date'25 o paro R04g ■-, N-th. R0e 〆 01 ``-4- 17 已2 To gate ■

Claims (1)

[Claims] The input signal is a parallel type A with a resolution of N bits (N is a positive integer).
A/D converter performs A/D conversion to obtain a first upper N-bit digital output, and a value obtained by D/A converting the first digital output of the N-bit parallel type A/D converter and the input signal. The value obtained by multiplying the difference by 2^N^-^1 by the N-bit parallel type A/
As the second input of the D converter, A/D conversion is performed by the parallel A/D converter to obtain a lower second N-bit digital output, and the upper first N-bit digital output and the lower 2 N-bit digital outputs are added with 1-bit overlap to obtain a (2N-1) bit digital code, and to further obtain the lower bits, the second N-bit digital output of the N-bit parallel type A/D converter is added. The difference between the value obtained by D/A converting the output and the second input of the N-bit parallel A/D converter is 2^
The value multiplied by N^-^1 is used as the third input of the N-bit parallel A/D converter and A/D converted to obtain a third N-bit digital output, which overlaps by 1 bit with the above addition result. The serial type converts the A/D converter a total of M times (M is an integer greater than or equal to 2) to obtain a digital output of (MN-M+1) bits. In the A/D converter, the parallel type A/D converter uses 1L from the A/D conversion result.
SB A parallel type A/D converter that outputs a small value as an output code, provided that the A/D of the N-bit parallel type A/D converter
If the conversion result is “0”, the output is “0”, and the N
Each comparator that makes up the bit-parallel A/D converter outputs “if the input voltage is greater than the comparison voltage of each comparator.
If the input voltage is smaller than the comparison voltage, it outputs “0”.
This is a comparator that outputs the above bit to the least significant bit only when adding the output code of the final parallel type A/D conversion when adding the upper bit and lower bit with 1 bit overlap to obtain the output code. N-bit parallel type A/
A series/parallel type A/D converter characterized in that a digital output code is obtained by adding the outputs of comparators whose comparison voltage is a reference voltage/2^N^+^1 among the comparators constituting the D converter.