RU1777242C - Digital-to-analog converting unit - Google Patents

Abstract

The invention relates to automation and computer engineering and can be used to control analogue actuators from a computer. The purpose of the invention is to improve the accuracy of conversion. The digital-to-analog conversion device comprises a register 1. Adders 2,3 and a digital-to-analog converter 4 are functionally interconnected. 4 ill.

Description

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The invention relates to automation and computer engineering and can be used to control analogue actuators from a computer.

Digital-to-analog converters containing current switches and a resistive matrix (1) are known.

The disadvantage of this device is the limited accuracy

The closest in technical essence is a digital-to-analog converter containing a standard n-bit DAC connected to a digital adder, one input of which is connected to the (n + t) -bit bus, and the other with the output of a t-bit counter, the input of which connected to a generator (2).

The known device, due to the pulse width modulation mode of the lower m-bits, improves the conversion accuracy. However, in some cases, pulse width modulation mode necessitates the use of a smoothing filter, which leads to poor dynamics and thereby limits the scope.

The purpose of the invention is to improve the accuracy of conversion.

This goal is achieved by the fact that the digital-to-analog conversion device containing the first adder, (p-2) bits of the first input of which are connected to the zero potential bus, (p-1) -bit outputs of the first adder are connected, respectively, with bits from the second to the n-th input of the digital-to-analog converter, the output of which is the output of the device, a second adder and a register are introduced, and the input bus of the device is connected respectively to the information inputs of the register, the clock input of which is connected to the clock the input of the device, the output of the (n + 1) th bit of the register is connected to the (n-1) th bit of the first input of the second adder, the bits from the first to the (n-2) th first input of which are connected to the output of the signed bit yes register, (n-1) -th digit of the first input of the first adder and the input of the sign bit of the digital-to-analog converter, the bit outputs from the second to the fifth register are connected respectively with the bits from the first to (n-1) -th second the input of the second adder, the bit outputs of which from the first to (n-1) th are connected respectively with the bits from the first on the (p-1) -th second input of the first adder.

In FIG. 1 is a functional diagram of a digital-to-analog conversion device of FIG. 2 (a, b),

3 (a, b), 4 (a.b) are graphs that explain the operation of the device.

The input bus of the device is connected to

(n + 1) -inputs of (n + 1) -bit register 1. (n-1) -bit output of register 1 is connected to (n-H) -bit first input of the first adder 2, (p-M ) -bit for register 1 output is connected to the lowest bit

the second input of the first adder 2, the remaining bits of which are connected with the first (signed) senior bit of the output of register 1 and with the lowest bit of the second input of the second adder 3. (n-2) bit

the second input of adder 3 is connected to the ground bus, (p-1) the outputs of the first adder 2 are connected to (p-1) the bits of the first input of the second adder 3, the outputs of which are connected to the device output through a digital-to-analog converter 4. The sign bit of the digital-to-analog converter is connected to the sign bit of the register output.

The operation of the device is as follows. To the (n + 1) bit input of the device, from the output of the code setter or from the control digital computer, a (n + 1) bit code is received with the addition of the nth bit. This additional code is written to register 1 by the SI clock. An adder (p-1) bit code is added to adder 2 with a second number that is a combination of the first and (n + 1) bits of register 1 and represents 0 .... 0 (n + 1) with a positive code or 1 .... 1 (n + 1) with a negative code. The result of addition from the output of adder 2 is fed to the (n-1) -bit first input of adder 3, the second input of which receives the number 0, ... 00 with a positive code in register 1 or 0 .... 01 with a negative code in register 1, the (n-1) -bit code from the output of the adder 3 is fed to the input of the DAC 4, at the output of which the corresponding voltage U appears

Figure 2 presents the characteristic dependence of the output voltage of the device on the code at the input of register 1 with zeroed (grounded) second inputs

adders. The abscissa represents the number of quanta of the lower n-th digit of register 1.

In FIG. Figure 26 shows a device error, calculated as the difference between the real and ideal characteristics. Thus, the error of the known device (prototype) reaches modulo

Urn

,

In FIG. The characteristic of the device with the zeroed second input of the adder 3, which in the positive area characterizes the efficiency of the adder 2, is presented.

In FIG. 36 there is a need in the field of negative numbers to raise the characteristic by one quantum m -. Last thing

carried out taking into account the second input of the adder 3, as shown in Fig, 4, where the error in the field of positive and negative numbers does not exceed modulo

. Comparing FIG. 46 from FIG. 26

2 ()

it can be seen that the proposed device in comparison with the prototype allows to reduce the error of the device by 2 times, and therefore to increase the accuracy of the device.

Claims (1)

SUMMARY OF THE INVENTION A digital-to-analogue conversion device comprising a first adder, p-2 bits of the first input of which are connected to a zero potential bus, p-1 bit outputs of the first adder are connected, respectively, with bits from the second to the n-th input of the digital-to-analog converter, the output of which is exit devices, characterized in that. in order to increase the conversion accuracy, a second adder and a register are introduced into it, and the input bus of the device is connected respectively to the information inputs of the register, the clock input of which is connected to the clock input of the device, the output of the (n + 1) -th bit of the register is connected to (n-1 ) -th bit of the first input of the second adder, bits from the first to the (n-1) th input of which is connected to the output of the sign digit of the register, the (n-1) th digit of the first input of the first adder and the inputs of the sign bit of the digital-analog converter, the bit outputs from the second to the n-th register are connected respectively with bits from the first to (p-1) -th second input of the second adder, whose bit outputs from the first to (p-1) -th are connected respectively with bits with first (p-1) -th second input of the first adder. U / the code Mr. -I  g s g-g / ; Oshi Zcha / V / w -Ј-. to-g-z- 4 Bg.2 and and / / the code / g At 1 I J V / o} Error /the code -,, trod ff) .4