SU1580538A1 - Device for phase automatic frequency control - Google Patents

Abstract

The invention relates to a pulse technique, in particular to digital computing, and can be used in the construction of controllers for magnetic disk drives. The purpose of the invention is to increase the reliability and simplify the device. The device contains a trigger, a counting device and the element is NOT. The second trigger, the second element NOT, the three elements OR - NOT, the AND element - NOT, the AND - OR - NOT element and the delay element are entered into it, and the counting device is made in the form of a counter with successive transfer. 2 Il.

Description

The invention relates to a pulse technique, in particular to digital computing, and can be used when building controllers of magnetic disk drives.

The purpose of the invention is to increase the reliability and simplify the device.

Figure 1 shows the functional diagram of the device; Fig. 2 is a graph of device states; FIG. 3 shows examples of code situations that explain the principle of operation of the device; figure 4 - timing charts of the device in all possible modes.

The device (figure 1) contains a counter 1, the element AND-NOT 2, the triggers 3 and 4, the elements NOT 5 and 6, the elements OR-NOT 7-9, the element AND-OR-NOT 10 and the element 11 delay. Triggers 3 and 4 are made according to standard schemes using the elements OR-NO 12 and AND-OR-NOT 13. The first input of the element 10 is connected by bus 14 to the first input of the element 7, the input of the element 5 and the information input 15 of the device. The first input element 2 is connected to the input 16 of the synchronization device, the output element 8 is connected to the first input of the trigger 3 and the output 17 of the device. The first to fifth outputs of the counter J are connected respectively by bus 18 to the first input of element 8, bus J9 with the second input of element 10 and the input of element 11i by bus 20 with the second input of element 8, bus 21 with the second input of element 7 and bus 22 with the third inputs of the elements 8 and 10.

The output of the element 10 is connected to the first input of the element 9, the output of which is connected to the second input of the element 2, the output of which is connected to the synchronization input of the counter 1. The first, second and third inputs of the installation of the counter 1 are connected to the bus 23 of the trigger 3 and the third input of the element 7, output which

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It is connected to the first input of the trigger 4, the output of which (bus 24) is connected to the second input of the element 9 and the fourth input of the installation of the counter 1.

The output of the element 5 is connected to the input of the element 6 and the bus 25 with the second input of the trigger 3. The output of the element 6 is connected by bus 26 to the third input of the trigger 3 and the second input of the trigger 4. The output of the element 11 is connected to the fourth input of the element 7.

The state graph of the device (Fig. 2) displays eight possible logical states of counter 1 and shows the directions of possible transitions between these states. Timing diagrams a, b, c, d (Fig. 3) clarify the principle of the device and display the signals at input 15 (diagrams a, Y; 6D; c, Ґ; r, Y) and output 17 (diagrams a, Z; 6; Z; B; Z; r; Z). The sequence of numbers shown in Fig.Z, display the sequence of numbers produced by the counter 1.

Timing diagrams e, f, g, i, i, k (Fig. 4) explain the operation of the device in all possible modes. Diagrams d, Ј; e, f; OK, Ј; er, Ј; and, Ј; k, Ј display the signals at the input 16 of the device diagram d, P; e, n ;, x, b; W, M; them; K, N - codes in the counter 1, diagrams d, Ґ; e, Y; OK, Ґ; s, y; H, Y; K, Y is the signal at the input 15 of the device, diagrams d, b; e, h is the signal on the bus 24, diagrams d, P; e, F; W, E; h, P is the signal obtained as a result of the logical multiplication of signals on buses 19 and 22 (at the inputs of element 10), diagram h, CH is the signal at the output of element 2, diagram k, 5 is the signal on bus 23.

The counting device is made according to the scheme of a counter with sequential transfer and has a size equal to 1 three. Tires 18–22 correspond to the inverse signal a of the lower order, the forward b and inverse b of the signals of the desired bit, direct with the inverse Tf signals of the higher order. If there are Log.O signals at the installation inputs of counter I (bus 23 and 24), i.e. at S h 0, the counter operates in the mode of adding one to the old contents. The unit is added on the negative edge of the CL signal at the output of element 2, i.e. I at the transition of this signal from the state Log.1 to the state Log.O. The signals Log.1 and Log.O are represented by high and low voltage levels respectively. If the counter overflows, it starts the counting again from the zero code (a b c 0). The operation of the counter in the natural counting mode corresponds to the cyclic shift of the absence of false positives of element 7.

The device works as follows.

The device is designed to produce at the output 17 a sequence of pulse signals Z having a certain phase relation with the pulse signals Y, arriving at the information input 15 of the device. In ideal cases, the signals Y should fall in the middle of the time intervals between the signals Z (Fig.3, a, b), i.e. the counter status correction is not performed if the Y signal is received at the moment when code 2 (010) or 3 (011) is present in the counter. Z signal is generated in those

from node to node (fig. 2) for pain-20 time periods, when in the counter

circle in the direction indicated by the arrows.

If, h 1, then the average bit (signal b) is forcibly set to the state of Log.1, and the other two bits remain unchanged. When the meter operates in the device, only two such situations are possible. In the first of these, the counter changes from state 000 to state 010, and to the second from state 001 to state 011 (FIG. 2). If h 0, S 1, then the counter is forcibly set to the state 001. When the meter operates as part of the device, a unique situation of this kind is possible: the transition from the 111 state to the 001 state along the external arc of the graph shown in Fig.2. The logic of the device is such that single signals S and h never form at the same time.

When the counter is working, its temporary suspensions are possible (for one period of the signal f), which are conventionally shown in FIG. 2 as cycles (three small circles in the upper part of Fig. 2). Such suspensions are achieved by generating a prohibition signal for the temporarily locking element 2 and preventing the CL signal from entering the synchronization input of the counter.

The delay element 11 compensates for the delay of the transfer of the transfer signal from the average to the highest bit of counter 1. If the transfer signal has a maximum delay equal to 10 not, then the minimum delay of element 11 can be chosen equal to, for example, 15 not. At the same time, the code 7 (111) is guaranteed.

If the signals Y arrive proactively or late (FIGS. 3, c, d), then the counter gradually adapts 5 to these signals, speeding up or slowing down the count by jumping over one of the states or pausing by one measure. As a result, the Z signals gradually acquire the desired phase relationship with the Y signals.

In Fig. 3, the first pulse Y falls on code 7 in the counter, therefore the counter does not encode in time the sequence sig0

 jumps to code 1, O. This leads to a shift5

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O. The counter responds again to the f ..

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Jumping to code 2, mine code 1 and thereby again shifting the time diagram of signals Z in the right direction. The third impulse Y hits code 1. The counter, min state 2, goes to state 3, continues the adaptation process, and finally, the fourth impulse Y hits code 2 - the adaptation process is completed. Subsequently, the counter operates in the natural mode (without any correction), and the Y pulses fall on code 2.

If the pulses Y begin to lag or overtake the counter, a corresponding smooth correction of its contents is made. In figure 3, the first impulse Y is late (hit code 6 in the counter), so the counter skips one clock cycle — for two adjacent time intervals

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the content remains equal to 6. Due to the time diagram shift received, the signaler Z next pulse is late not so much as the first one — it hits code 5, which also does not change for two cycles, the next pulse Y hits code 4, the counter again Chortormage

Finally, the fourth pulse falls in the middle of the interval between the Z pulses, which is required.

The period of the signal f applied to the synchronization input 16 of the device is selected 16 times smaller than the minimum period T of the repetition signals Y (signals Y depending on the information read from the magnetic disk come with a period T, 1.5 T or 2 T). Further, it is assumed that the signal Y is related to the period of the signal f.

Eight situations are possible according to the number of possible codes in the counter for which the pulse Y falls. In FIG. 4, d, the first situation is shown in which the pulse arrives at the device input 15 at the moment when there is a zero code (N 0) in counter 1. According to FIG. 2, in this case, the counter must go from state 000 to state 010 along the external arc of the graph, mine state 001. This process proceeds as follows. By the moment the pulse Y arrives,, C 0. b1 0, therefore, the pulse Y passes through element 7 and sets trigger 4 to one (h 1), which causes counter 1 to go to state 010. The signal hl affects the input element 9, a Log.O signal is generated at its output, prohibiting the transmission of a pulse f to the synchronization input of counter 1. In this case, condition F 1 is satisfied.

The considered process ends with the removal of the signal Y, as a result, the signal h 1 is taken, and then the counter each time adds one to its old content along the positive edges of the signal f. It can be seen from the diagrams shown in Fig. 4 d that the N codes in the counter do not change in the same way as in the natural counting order (see the upper row of numbers: 7.0,1,2.3

FIG. 4, e shows the second situation in which the pulse arrives at the moment when code 1 is hit in the counter 1. This situation is

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logical previous. A transition is made from code 1 to code 3 with code 2 omitted.

Figure 4, g shows the situation in which at the moment the signal Y N 2 arrives, thanks to the fulfillment of condition F 1, a Log.O is generated at the output of element 10 and the signal Y does not prevent the signal f from passing to the CL input of the counter. Thus, the natural count continues.

Figure 4, 3 shows the situation in which at the moment the signal Y arrives. By the time the signal arrives. YF 1, therefore, the next positive pulse f causes the unit to be added to the contents of the counter and code 4 is set in it. At the same time, the condition and the signal, passing through elements 10 and 9, are satisfied, cause the Log.O signal to be removed from the synchronization input of the counter (see short negative impulse in diagram 4, h. CL). After the end of the positive pulse f, the signal Y is taken off, and later the counter continues to operate in the mode of adding units to its content.

4, and illustrates the operation of the device in those cases where it is necessary to start up one clock cycle. These situations correspond to the arrival of the signal Y at those times when the code 4, 5 or 6 is present in the meter (see cycles shown in FIG. 2). All three situations are characterized by fulfilling the condition F 0 so that the signal Y, passing through elements 10 and 9, prohibits the passage of the next pulse f (in FIG. 4, and this pulse is hatched) to the synchronization input of the counter. As a result, the counter pauses the count for one cycle, which is what is required.

Figure 2 shows the situation in which at the moment the signal YN 7 arrives. In this case, trigger 3 is set to one state (S 1), and element 7 is locked by signal S to prevent subsequent triggering of trigger 4 and distortion of information in the counter. . Since 3 1 and, the counter is set to state 001 (see the arc connecting the nodes 111 and 001 to Fig. 2). At the end of the pulse Y, signal 5 is removed, and the counter continues to operate in the

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Claims (1)

Claim A device for phase-locked loop containing a trigger, a counting device and a NOT element, whose input is connected to the information input of the device, characterized in that, in order to increase the reliability and simplify the device, a second trigger is introduced into it, the second element is NOT, the three elements are NOT-NOT, the element Y-NOT, the element AND-OR-NOT and ele- _{) 5} delay, and the counting device is made in the form of a counter with sequential transfer, the first input of the element AND-OR-NOT connected to the first input of the first element OR-NOT ^ with the input of the first e NOT element, the first input of the AND-NOT element is connected to the synchronization input of the device, the output of the second OR-NOT element is connected to the first second input of the AND-OR-NOT element and to the input of the delay element, with the second input of the second element -OR-NOT, with the second the input of the first OR-NOT element, with the third inputs of the second OR-NOT element and the AND-OR-NOT element, the output of which is connected to the first input of the third OR-NOT element, the output of which is connected to the second input of the AND-NOT element, the output of which is connected to counter synchronization input, first, second and third inputs The arrangements of which are connected to the output of the first trigger and to the third input of the first OR-NOT element, the output of which is connected to the first input of the second trigger, whose output is connected to the second input of the third OR-NOT element and to the fourth input of the counter installation, the output of the first element is NOT connected to the input of the second element is NOT and with the second input of the first trigger, the output of the second element is NOT connected to the third input of the first trigger and the second input of the second trigger, the output of the delay element is connected to the fourth input of the input of the first trigger and 'with the output of the device, the first to fifth outputs of the counter are connected respectively to I 580538 6 then 11 s s s in JOf f 3 ¥ 0 in s / s s t s 1 t s * ”_L _______ ΓΊ__P _______ P ____________ At t in) 6 That 19 3 4 J 6 that 1934567 0123456 701934? _L ______ p ______ p ......... p 6 T f 9 3 ... 5 6 7 O g 3 ... S 6 t 01 3 ... 5 6 7 Of 2 3 ... 5 6 7 * _Л ____ п_ - _{f {} - \ ~ T; 1.3 g or 9 g! <tVi.3 L - Μ, α