SU1575204A1 - Device for conversion of matrices - Google Patents

Abstract

The invention relates to automation and computing and can be used in specialized matrix computers. The aim of the invention is to expand the functionality of the device by calculating the determinant of the reversible matrix. In a device containing a clock, a trigger, a counter, input and output blocks, and a computing block, a matrix inversion method based on the Gauss-Jordan algorithm is implemented. A modification of the traditional algorithm consists in rearranging the rows and columns at each step of the recurrent matrix inversion procedure. 6 Il.

Description

The invention relates to computing, is intended to perform operations associated with the inversion of matrices, and can be used in specialized information processing devices in solving problems that are reduced to the effects on matrices.

The purpose of the invention is to extend the functionality by calculating the determinant of the reversible matrix.

Figure 1 is a diagram of the proposed device for reversing arrays; figure 2 - block diagram of the input; on fig.Z - diagram of the computing unit; figure 4 - diagram of the output unit; figure 5 - scheme of the arithmetic unit; figure 6 - diagram of the switch.

The device contains a clock pulse generator 1, trigger 2, direct output 3 of trigger 2, reverse output 4 of trigger 2, counter 5, output 6 of counter 5, device group of inputs 7, input bpok 8, computing unit 9, second group of information inputs 10 of block input unit 11 output group of outputs 12 devices. The input block 8 contains (N +1) multi-plexors 13, (N4 + l) elements And 14. Computing unit 9 contains (N + 1) registers 15, multiplier 16, (2N-1) divisors $ 17 (N-1 ) inverters 18, (N-1) 4 arithmetic nodes 19, switch 20, (N2 + l) registers 21. Output unit 11 contains () elements And 14. Arithmetic node 19 ij (where i, j 1, N-1) contains multiplier 22, adder 23.

The device implements an algorithm for reversing the matrix on the order of N, based on the exclusion method. The inversion of matrix A of order N occurs in N iterations. At each iteration

cl

4 SL GO

A new matrix A is computed (n, where n is 1, N, as follows

four

Here A-A 1- If I LJ

- the original reversed matri, (MP ha V C, j J

ca. To calculate the determinant of the matrix A, an additional element is introduced.

 cop

one

0 and at each iteration, in parallel with the calculation of the intermediate matrix AP, the value of a

"ABOUT

where n 1, n, as follows

in the following way:

g

, ("-)

1.1

det A

(}

When the device is turned on, trigger 2 is set to O, 3

those. direct output

oh and on the return output

N (it

trigger 2 set4

trigger 2 is set. The counter 5 is set to O, the output 6 of the counter 5 is O. The output 6 of the counter 5 is set to 1 only when the contents of the counter 5 change from O to 1. In all other cases, the output 6 of the counter 5 is O. The device is ready to work.

The device works as follows.

From the output of the generator 1, the clock pulses are fed to the input of the trigger 2, the clock pulse, as a result of which the trigger 2 changes its state to the opposite, t. on the direct output 3, the trigger 2 is set, on the reverse output 4 of the trigger 2 is set O. The contents of the counter 5 are incremented by 1 only when the forward output 3 of the trigger 2 is set to 1, therefore in the first clock cycle in the counter 5 it is set to 1. If counter 5 is written (N-1), then when setting 1 to

0

0

five

0

five

The direct output of the trigger 2 is set to O. At the output 6 of the counter 5, set 1, which is connected to the first control input of the input unit 8 and from the first control input to the control inputs of the multiplexers 13, which operate as follows: control input 1, then the output passes data from inputs 7; if at the control input O, then the data from the inputs 10. Due to the fact that the control inputs of the multiplexers 12 are fed 1, then from the inputs 7 they are passed

baths and (0 (0 (0 given afl, a, a, ..., aNN

and,

 -and chg

Since from the direct output 3 of the flip-flop 2, the control inputs of the elements AND 4 of the input block 8 and the clock inputs of the registers 15 are fed to 1, the data arrive at the information inputs of the computing unit 9 and are written to the registers 15, and the register a is written to the register 15, and in register 15, j, where i, j ment aW.

, N, EleDale e at the output of multiplier 6

(1 a and recorded

ii

formed a (°

in the register 21. At the output of the divider 17, the switch input 20 is formed and fed to 1.1. At the output of the divider 17; where i 2, and, forms ((L, (

with. , / а1 (, at the output of the solvent is 7-. where j N + I,, form - l (crt / „(ot

Routes

. five

Nfl

and enters

j - N + 1. 1 input of the switch 20. At the output of the inverter 58 (, where

i

- s

(about)

 1, N -1, is generated -a. / atl

i t t ui

0

0

and arrives at l.i +1 output of switch 20 and at the first inputs of arithmetic nodes 19} where j 1, N-. Simultaneously, the clock pulse generator 1 generates the next 5 clock pulse, which, arriving at the input of the trigger 2, sets it in the opposite state, i.e. On the direct output 3, the trigger 2 is set to O, and on the reverse output 4 of the trigger 2 is set to 1. From the direct output 3 of the trigger 2 O, entering the input of the counter 5, does not change its content, the output 6 of the counter 5 is present O.O on the direct output 3, the trigger 2 does not allow information to be recorded through the input block 9 into registers 15, 1 from the reverse output 4 of the trigger 2 is supplied to the clock inputs of the arithmetic 5

nodes 19 and synchronizes arriving at their information inputs

data. Output arithmetic I

knot 19- ;, where i, j 1, N-1, form- Y (o + (o). (o), “,,..

/ ru and h,. . „

m.jtf -n, i 1, jti,

and enters the i + I, j + 1 input of the switch 20. From the switch 20, the data enters the information inputs of the registers 21 (Fig. 6) and is written to them. Thus, in the register 21 „

recorded a

M

in register 21

i.J

where i, j IjN, is recorded AF. Clock pulse generator 1 generates a third clock pulse, which is fed to the counting input of trigger 2, as a result of which the forward output 3 of the trigger 2 is set, and the reverse output 4 of the trigger 2 is set to O. The content of the counter 5 becomes 2, the output 6 of the counter 5 - O. From the direct output 3 of the flip-flop 2 1 is fed to the clock inputs of the registers 15 and 21 and to the control inputs of the elements AND 14 of the block 9. From the output 6 of the counter 5 O, it is fed to the control inputs of the multiplexers 13 of the block 9, as a result reading from registers 21 occurs, data from which is fed to the information inputs 10 of the input block 8. Through the multiplexers 13, the data passes from the inputs 10 and then passes through the elements AND 14 of the input unit 8 and enters the inputs of the register 15. The device then works similarly to the first clock cycle. On the 4th, 6th, (2N} -rM cycles

the device works similarly to the second clock; on the 5th, 7th, ..., (2N-1) th cycles - similar to the third cycle. At the end of the clock in the register 21ffnpHcyT Yu about

a

those. det A. In regist

pe 21; tj, where i, j 1, N; a1: Y, an element of the desired reversed matrix A. The elements of the following matrix B to be addressed can be fed to the inputs 7 of the input block 8 at the 2N + clock. The generator of 1 clock pulses produces (2N + l) - & clock pulse that arrives at the counting input of trigger 2. As a result, At output 3 of trigger 2, 1 is present, and therefore the contents of counter 5 changes from 0 to 1 and, therefore, output 6 of counter 5 contains 1, thus the elements of the new matrix B with

75204 6

inputs 7 of input block 8 through multi-terminals 13 and elements 14 of input block 8 are written to registers 15 of computing unit 9, and from registers 21 through elements 14 of input block 11, elements of the first edited matrix A are read. At the (4N + 1) th cycle at the outputs of the 12th output unit at 10

-ii

Claims (1)

there are no elements of the matrix .J ar - a, tiv from stm. . l 2 | 15 A device for reversing matrices containing an input block, an output block, a clock pulse generator, a trigger, a counter, the output of which is connected to the control input of the output block and the first control input of the block I, Q yes, the information inputs of the first groups of which form a group of N + 1 device inputs (N is the dimension of the inverted matrix), the group of N4 + l outputs of which is formed by the group  the outputs of the output unit, the output of the clock generator is connected to. the trigger input, the direct output of which is connected to the counter input of the counter, characterized in that, in order to expand the functional possibilities by calculating the determinant of the inverted matrix, a computing unit is entered into the device, the 1st information input of which (i 1, N1) connected to the same output of the input block, the i-th information input of the second group of which is connected to the information input of the output block of the same name and the output of the computing block, the first control The 40th input of which is connected to the second control input of the input unit and the forward output of the trigger, the inverse output of which is connected to the second control input of the computing one. t 45 blocks containing N +1 input and N +1 output registers, a multiplier, 2N-1 dividers, N-1 inverters, a matrix of (Nl) x (Nl) arithmetic nodes and a switch, the information input of the 1st input register being the i-th information input of the computing unit The i-th output of which is the output of the 1st output register, the output of the first input register is connected to the first input of the multiplier, the output of which is connected to the information input of the first output register, the output of the second input register is connected to the second input of the multiplier and the first inputs of all dividers are the second input of the j-ro divider (j 2, N) connected to the | output (j + l) -ro of the input register, the second input of the second divider (, 2N-1) is connected to the output ( N (KN) +2) is the input register, the output of the first divider is connected to the first switch of the switch, the jth input of which is connected to the first information input (t,;) -) then the arithmetic node (N-1) and exit (jl) -ro in-. the controller, whose input is connected to the output of the j-ro divider, the output of the K-th divider is connected to the (N () + 1) th input of the switch, the 1st output of which (1. connected to the information input (lH) -ro of the output register , the second information input of the (m, n) -th arithmetic node (, Nl) is connected to the second input of the (n + N) -ro speaker, the third information input and output of the (m, n) -ro arithmetic node five 0 la connected, respectively, to the output (mN + 2 + n) -th input register and (ty + 1 + n) to the input of the switch, the write enable inputs of the input registers interconnected are connected to the read enable inputs of the output registers and connected to the first control input of the computing unit, the second control input of which is connected to the clock inputs of all arithmetic nodes, each of which contains a multiplier, and an adder, and the first and second information inputs of the multiplier are respectively The inputs of the arithmetic unit whose clock input is the clock input of the multiplier, the output of which is connected to the first input of the adder, the second input and output of which are respectively the third information input and the output of the arithmetic node. to Fig 2 Fg / g4 one n 3-r F.5 Editor S. Lisin Compiled by K. Kukharenko Tehred M. Khodanich Proofreader M. Kucher va Order 1786 Circulation 568 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology CQCP 113035, Moscow, Zh-35, 4/5, Raushsk nab. Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 6 Subscription