SU1562908A1 - Frequency multiplier - Google Patents

Abstract

The invention relates to computing and can be used in frequency information processing devices. The aim of the invention is to expand the field of application by enabling the simultaneous correction of the conversion characteristics of the primary and secondary transducers. The frequency multiplier contains the control node 1, the first counter 2, the first register 3, the adder 4, the second counter 5, the delay element 6, the clock pulse generator 7, the frequency divider 8, the correction code generation unit 9, the second register 10 and the memory block 11, interconnected functionally. The control unit 1 comprises two formers 12, 13 pulses, two elements AND 14, 15, a delay element 16 and an element OR 17 with corresponding functional links. 1 hp f-ly, 2 ill.

Description

The invention relates to computing and can be used in frequency information processing devices.

The aim of the invention is to expand the field of application due to the possibility of simultaneous correction of the conversion characteristics of primary and secondary transducers.

FIG. 1 is a functional diagram of a frequency multiplier; FIG. 2 is a functional diagram of a correction code generation unit.

The multiplier contains a control unit 1, a first counter 2, a first register 39, an adder 4, a second counter 5, a delay element 6, a clock generator 7, a divider 8 hour ™ divider, a correction code generation unit 9, a second register 10, and a memory block, functionally interconnected 9, where the control unit 1 contains the first 12 to the second 13 formors of the impulses, the first 14 and the second 15 AND elements, the 16 delay element and the OR 17 element with the corresponding functional links.

- Correction code generation unit 9

contains the first counter J8, the pulse generator J9, the second counter 20, the element OR 21, m decoders 22 and the frequency divider 23, which are functionally interconnected,

The frequency multiplier works as follows.

The pulses of the input sequence FK arrive at the first input of the control unit 3, where the pulse generator 12 is fed to the input, which produces pulses along the anterior front pulse of the input sequence F. The pulse former 13 provides for the formation of pulses at its output with some delay. relative to the pulses from the output of the shaper 12 pulses, i.e. the pulses at the outputs of the formers are shifted one relative to the other by an interval of time equal to ,. This is necessary so that by the time of the formation of the second control pulse the transient process is complete.

in the corresponding elements and nodes, i.e. to ensure reliable operation of the device (excluding races in the control circuits).

Elements 14 and 15, delay element 16, and also OR element 17 provide synchronization of control pulse sequences from the output of Shaper 12 pulses with the pulses of Correction Code Formation 9, received at the second input of control unit 1. Such synchronization is necessary in order to exclude the possibility of malfunction of the multiplier. In the case when the pulses from the output of the pulse generator 12 and the synchronization output of the correction code generation unit 9 are formed simultaneously, the element 14 is closed (via the inverse input), and the And 15 element is open. In this case, the impulse that is formed at the output of the AND element 15 passes through the delay element 16 and further through the OR element 17 to the output of the control unit 1. In any other cases, the element AND 4S is open and the element AND 15 is closed and, therefore, the signal from the output of the Shaper 12 pulses passes through the elements AND 14 and OR 17 to the output. unit 1 control "

The delay provided by the delay element 16, and the time interval C, are selected based on the conditions

jr l / in

 2 SE (Cb ° a) C1)

five

where (Јen ") the total switching time of the register 1 0 and memory block 11

When conditions (1) are fulfilled, the signal at the control input of the adder 4 appears only after the transient (switching time of the corresponding elements) in the additional register 10 and memory block 11 is over.

In counter 2 (the number of pulses), during a time interval equal to the period T to the pulse sequence Fje, a code is generated, defined as

and

N

t "

 T "-Fn.M

where FQ is the frequency at the generator output 7 clock pulses; M is the division factor of the frequency divider 8.

The signal from the second output of the control unit 1 is fed to the control input of the adder 4, and the sum M of two codes is formed in the adder - the code equivalent NT of the pulse period of the input signal and the correction code M supplied to the adder from the outputs of the memory block 11, i.e.

NЈ

NT + tx

N.

Then, the pulse from the first output of the control node 1 contents the sum of the torus 4 is rewritten into register 3. The code from register 3 is rewritten into counter 5 with each pulse generated at the output of the high bit of the counter. The period of occurrence of pulses at the output of counter 5 is defined as

T.- (NT + NK) -T0.

The pulses from the output of counter 5 are fed to the output of the multiplier, and also pass through delay element 6 and provide a copy of the contents of register 3 to counter 5. Thus, the pulse frequency at the output of the multiplier is determined by the expression

g, F0

1M N + N,

Since N.

NT

N,

(Where

N is the corrected value of the code equivalent of the period Tx of the pulse of the input signal), then the record is valid

-i

where t

Nze

XK

TH -F M,

H o /

the period of impulse correction (without systematic error) of the input sequence F corrected with a given accuracy for a given value of the input influence quantity (temperature).

Thus, the pulse frequency at the output of the multiplier is equal to

M

 I

T -f kk o

 F M UK x h

Correction codes are generated as follows.

The pulse frequency signal carrying information about the destabilizing value (for example, temperature), which must be compensated, comes from the corresponding sensor to the input of the correction code generating unit 9. During a specified time interval TC, defined

5629086

the conversion factor of the frequency divider 23, the pulses of the input signal are fed to the input of the counter 18 (the number of pulses). The state of the counter 18 is monitored by a series of decoders 221 ... 22, each of which is tuned to the appropriate portion of the dependence of the temperature sensor (temperature ' 0 is the pulse frequency). Egpi, i decoders are triggered for a given TU, then i pulses arrive at the input of counter 20 (pulses) through the OR 2 element. Code,

15 Forming in the counter 20 (pulses) during the TC, determines the number of the correction area. This code is fed to the outputs of block 9 of the correction code former, which are connected to

20 information inputs of the register 10. The first pulse, Forming at the output of the former 19, at the time of the windows

TU provides a census of the contents of counter 20 (pulses) into a register of 10 multiplier. The second pulse, which appears at the output of the imager 19 with a certain delay Ј, selected from the condition of a reliable census of information from the counter 20 (30 pulses) into the register 10 of the multiplier,

sets the counters 18 and 20 pulses to the zero state, i.e. prepares them for the next cycle of work.

The outputs of register 10 are connected to the address inputs of memory block 1I, whose cells contain the corresponding correction codes Nk. Each i-th site has its own code

35

N

to;

calculated from the condition of ensuring the minimum (allowable) error of multiplication within each of the correction sections. Therefore, the correction is performed on the basis of a piecewise-step approximation method. The volume V of the memory block 11 depends

on the number of correction plots and codes

m

N4 correction, i.e. V 21-n. Input

corrections, it is possible to ensure high accuracy of multiplication in a wide range of influencing quantities (temperature). Thus, the frequency multiplier performs the correction of the conversion characteristic of the primary and secondary transducers, the output of which is the pulse frequency. This greatly expands the scope of application.

The multiplier is compared to the known one. The multiplier performs the redprocessor processing of information, which determines its higher technical and economic indicators.

formula of invention

Claims (2)

I. Frequency multiplier, which contains d clock generator, divide frequency, first and second counters, first register, delay element, and memory block, with the clock pulse output connected to the information j input of the frequency divider and counting input the second counter, the packaging inputs of which are connected respectively to the bit outputs of the first register, the output of the second counter-2Q transducer is connected to the output of the multiplier and the input of the delay element whose output is connected to the enable input of the parallel recording of the second The output of the frequency divider is connected to the 25 counting inputs of the first counter, which is characterized by the fact that, in order to expand the application area due to the possibility of simultaneous correction of the conversion performance of 30 primary and secondary measurement transducers, the Correction Code Formation block is entered into it, the second register , the adder and the control unit containing the first name-pulse generator, whose input is connected to the information input of the control node, the output of the first pulse-generator is connected to the input of the second the pulse former and the first inputs of the first and second elements And, the second inputs of which are connected to the control input of the control unit, the output of the second pulse generator, is connected to the first output of the control unit 45, the output of the first element And is connected to the first input of the OR element, the output of the second element AND is connected to the input of the delay element, the output of which is connected to the second input of the CQ element OR, the output of which is connected to the second output of the control unit, at -. than the information input of the control node is connected to the first information input of the multiplier, the second information input The input of which is connected to the information input of the correction code generation unit, the bit outputs of which are connected respectively to the information inputs of the second register, the bit outputs of which are connected respectively to the address inputs of the memory block, the outputs of which are connected respectively to the inputs of the first group of the adder, the inputs of the second group which are connected respectively to the bit outputs of the first counter, the bit outputs of the adder are connected respectively to the information inputs of the first register A tra, the recording enable input of which is connected to the installation inputs of the first counter and frequency divider and to the first output of the control unit, the second output of which is connected to the control input of the adder, the output of the clock generator is connected to the clock input of the correction code generation unit, the synchronization output of which connected to the write enable input of the second register and the control input of the control node, 2. A multiplier according to claim I, about tl and - due to the fact that the block for generating the correction code contains the first and second counters, m decoders (where m is 1,2,3, ...), the OR element, the frequency divider and the driver pulses, and the counting input of the first counter is connected to the information input of the correction code generation unit, the clock input of which is connected to the input of the frequency divider, the output of which is connected to the input of the pulse generator, the first output of which is connected to the synchronization output of the correction code generation unit pulses connected to the inputs of the installation of the first and second counters, the bit outputs of the first counter are connected respectively to the inputs m of the decoders, the outputs of which are connected to the inputs of the OR element, the output of which is connected to the counting input of the second counter, the bit outputs of which are bit outputs block code generation correction.