SU1555891A1 - Device for isolating of clock-pulse oscillation in autocorrelation receiver - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve the accuracy of the allocation of clock oscillations and simplify the device. The device contains an amplifier-limiter 1, a selector 2 of the front of the input signal, a shaper 3 RF stabilizing oscillations, an EL 4 block, a sampling unit 5, a phase margin selector unit 6, a frequency divider 7, a phase autonomous frequency control unit 8, a driver of 9 single pulses, discrete block 10 delay. The goal is achieved by introducing a delay selection block 11, with which, depending on the type of phase jump in the transmission and the law of change of the carrier frequency phase (the number of reception sections), the first pulse is selected by the driver 9 from each pulse packet arriving at its input true value of recovery moments. 1 il.

Description

The invention relates to telecommunications, in particular to the transmission of discrete Hb ix signals over channels of the tone frequency using multipositional relative phase modulation and can be applied in telegraphy and data transmission.

The aim of the invention is to improve the accuracy of the allocation of clock oscillations and simplify the device.

The drawing shows a structural electrical circuit of a clock oscillator for an (autocorrelation receiver).

The device contains an amplifier-limiter 1, a selector 2 of the front of the input signal, a shaper 3 high-frequency stabilizing oscillations, an element 4, a sampling unit 5, a phase selection block (FZ) 6, a frequency divider 7, a phase-locked frequency modulator 8 (F1HC), a driver 9 single pulses, a discrete delay unit 10 and a delay selection unit 11.

The clock oscillator operates as follows.

Phase-manipulated signal through the amplifier-limiter 1 is fed to the input of the selector 2 fronts of the input signal, which generates short pulses corresponding to the fronts of the input signal. These pulses arrive at the input of sampling unit 5, to the installation input of which impulses from the output of the PLL unit 8 correspond to the middle of the elementary premises of the phase-shifted signal. These pulses in the sampling unit 5 are used to extract from the pulses generated by the selector 2, the pulse closest in time to the pulse arriving at the installation input of sample block 5 and following it.

This pulse, which is a pulse of the input sequence and is in the middle of the most noisy-protected part of the elementary output signal of the output of 2 Fronts of the input signal, and the signal from the output of the FZ selection block 6, the installation of which, like the frequency divider 7, occurs in the middle part of the received parcel, when the process of increasing the phase, regardless of the law of its growth, is already completed.

At the same time, before the new phase jump in the transmission, the pulses from the selector 2 and the oscillation from the output of the FZ selection block 6 are in a constant phase relation. At any phase jump on the transmission at the output of the element 4, there appear packets of pulses, the beginning of which coincides with the moment of the phase change of the given parcel relative to the previous one by an angle exceeding the phase margin. These packets appear to be necessary at any phase jumps in the transmission, since the comparison of the input signal occurs with a minimum zone of phase margin.

At the output of the single pulse generator 9, a first pulse is emitted from each pulse packet arriving at its input. This impulse is close to the true value of recovery moments (ZMV) with a minimum phase jump in the transmission and a linear law of change of the phase of the carrier frequency and significantly ahead of the true ZMV at maximum phase jumps and with a nonlinear law of change of the phase of the carrier frequency.

Consequently, depending on the type of phase jump in the phase and the law of change in the phase of the carrier frequency (number of transients), it is necessary to delay this pulse to the true value of the MIT. This task is performed by the discrete delay block 10 and the delay select block J1.

Discrete discrete delay unit 10 is a counter with a reset, the clock input of which is connected to the second output of the driver 3, and the setup input to the output of the generator

ki of the received signal is used by the clock 9. The counter is set

as a gate for the operation of a decoder. This pulse sets the frequency divider 7 and the FZ selection block 6 to the initial state. The clock input of the divider 7 receives pulses from the driver 3.

On the element 4, a phase comparison of the position of the pulses of the input sequence occurs;

the initial state of each pulse occurred at the output of shaper 9. This pulse is the beginning of the delay counting. The counter, performing the role of a discrete delay block I0, has a certain number of outputs that can be considered as from the delay line. The specific value of the number of taps m depends on the three

five

the initial state of each pulse that occurred at the output of the imaging device 9. This pulse is the starting point of the delay. The counter, which acts as a discrete delay block I0, has a certain number of outputs that can be considered as taps of the delay line. The specific value of the number of taps m depends on tre5,

The accuracy of the clock selection, the phase modulation ratio, and the number of intercept channels of the tonal frequency channel.

In general, at the first output of the discrete block 10, the delay is minimal and equal to zero, and at the last output it is maximum and equal to half the duration of the elementary dressing (maximum rise time of the carrier frequency base with a nonlinear law of variation).

Selecting a high clock frequency at the remaining outputs of the discrete delay unit 10, get with great accuracy the entire set of necessary time delays. The higher the clock frequency and the greater the outputs of this block, the more accurately you can bring the pulse allocated by the shaper 9 to the true optimal MPS. Consequently, regardless of the magnitude of the phase jump in the transmission and on the law of change in the phase of the carrier frequency at the reception at one of the outputs of the discrete delay unit 10, a true DFV for a given phase jump always occurs. It is this output that must be connected to the input of the PLL 8.

This task is performed by the block 11 of selection of the delay under the action of control signals, which are used as the output signals of the decoder. This is possible due to the fact that there is a one-to-one correspondence between the F jumps in the transmission and the output signals of the decoder. The decoder output signals in parallel code are multi-bit signals with the number of bits log, n. Therefore, the maximum number of control inputs of this device is also equal to Iog2n, where n is the number of positions of the multipositional phase modulation.

I

558916

Claims (1)

The invention of the Tactical oscillator in an autocorrelation receiver, comprising a series-connected input amplifier-limiter, an input edge selector, an And element and a single pulse former, as well as a block samples, to the input of which the output of the front-edge selector is connected, and the output of the sample block is connected to the installation input of the phase reserve selector and to the set input of the frequency divider, to the clock input of which the first output of the high-frequency stabilizing oscillator is connected, and the outputs of the frequency divider are connected to the corresponding information inputs of the phase reserve selection block, the output of which is connected to another input of the element I, the second output of the high-frequency stabilizing generator 5 oscillations are connected to a clock input of a discrete delay unit, and a phase locked loop (PLL), the output of which is connected to the setup input of the sampling unit and 0 to another input of the single pulse generator, which differs from the fact that, in order to improve the accuracy of the selection of the clock oscillation and simplify the device, a delay selector unit is inserted, while the output of the single pulse generator is connected to the setup input of the discrete delay unit and to one of the inputs of the delay selector unit, to 0 to the OTHER inputs of which the corresponding outputs of the discrete delay unit are connected, and the output of the delay selector unit is connected to the input of the PLL unit, with the control inputs of the unit The 5 delay selections are the control inputs of the device. five