SU1343558A1 - Apparatus for extracting clock oscillation in self-correlation receiver - Google Patents

Abstract

The invention relates to the field of telecommunications and reduces jitter output cycles. The pulses at the output of the discrete delay unit 13 are delayed with respect to the impulses at the input of this unit 13 that caused them to appear for the duration of the elementary dressing. These pulses are exactly the equivalent of a significant recovery moment at any phase jump in a multiple phase switch. Next, they arrive at the input of the block 9 phase-locked loop. At the same time, at one output, which is the clock output of the device, the jitter of the output cycles of the device is reduced, and at the other output more than npaBlmbHo, the impulse of the elementary dressing is determined, which controls the operation of the sampling unit 4 and the blocks 8 and 10 prohibitions. As a result, the noise immunity of the autocorrelation receiver is increased. 2 pcs. Tact. Bw f Page 2 ЖИИ to the decoder)

Description

The invention relates to telecommunications, in particular to the transmission of data signals over the channels of the tone frequency and using multipositional relative phase modulation, and can be applied in telegraphy and data transmission.

The purpose of the invention is to reduce the trembling of code cycles.

Fig. 1 shows a structured electrical circuit, a device for allocating a clock oscillation in an autocorrelation receiver; figure 2 - timing diagrams illustrating the operation of the device.

A device for allocating a clock oscillation in an autocorrelation receiver comprises an amplifier-limit. Ij differentiation unit 2, element I 3 ;, sampling unit 4, additional

To elements And 5

P

(K - - 1,

n is the number of phase positions of the multiple modulation), frequency divider 6, shaper 7 high-frequency stabilizing oscillations., block 8 prohibition, block 9 phase-locked loops (PLLs), additional K prohibition blocks 1C. to s element SHS 11, block 12 of the choice of the phase margin, block 13 discrete delay with the ban.

The device works as follows.

The phase-shift keyed signal arriving at the input of the device (Fig. 2a) after amplification and limitation by the output limiting amplifier 1 (Fig. 26) 5 enters differentiation unit 2, which forms short pulses corresponding to the fronts of the input signal (Fig. 2c). pulses are fed to the input of the 4th sample. The installation inputs of block 4 from block 9 of the PLL receive the impulses, the pulses corresponding to the middle of the elementary premises of the phase-shift keyed signal (Fig. 2d).

By these pulses, block 4 of the sample is used to separate from the pulses formed by the differentiation unit 2, the impulse closest in time to the impulse arriving at the installation input of the sampling unit 4 and following it (Fig. 2e).

These pulses, being the impulse of the input sequence and being in the middle of the most noise-free part of the elementary send of the received signal, are used as a building block for the operation of the decoded circuit: H: i.

frequency divider 6 in the initial state. In the initial state, the edge pulses of the input sequence correspond to the fronts of signals from the outputs of frequency divider 6.

The clock input of the divider 6 receives pulses from the driver 7 high-frequency stabilizing oscillations. The outputs of the frequency divider 6 connected to the decoding circuit are the information outputs of the device. The number of outputs depends on the modulation rate.

The principle of operation of the above nodes of the device, as well as block 9

PLL and blocks 8 and 10 of the ban, similar to the work of the corresponding nodes of the known device. The operation of the 9 PLL unit, one of the outputs of which is the clock output of the device,

the significant momentum recovery pulses (MIT) are controlled.

The principle of the separation of the ZMV is that, in the elements And 3 and 5j.

pulses of the input sequence, coming from differentiation unit 2, with oscillations generated by the phase margin selection unit 12.

Installing the block 12 phase selection

the stock, as well as the frequency divider 6, occurs by the pulse generated by the sampling unit 4 in the middle part of the received dressing, when the phase growth process is already completed.

before the new phase jump in the transmission, the pulses from the differentiation unit 2 and the oscillation block 12 select the phase reserve in a constant phase ratio.

The phase reserve selection unit 12 oscillates at its outputs with a frequency equal to the carrier frequency of the input signal, with zones equal to the module of the phase jump in the transmission, so that at the time of installation the input signal pulses are in the center of these zones, i.e. for each of the two equal phase jumps on the transmission, the phase margin formed

block 12 of the choice of the phase margin will be equal to half of the head of the jump of these

The number of outputs in block 12 of the choice of phase margin is half

the number of phase positions with multiple phase modulation. With double relative phase modulation (DOPM) there will be 2 of them, with three times relative phase modulation (TOFM) - 4, and zones formed by block 13 with DOFM will be 45 ° at the first output (phase reserve + 22.5 °, fig. 2e ). and at the second exit 135 (phase margin ± 67.5 °, fig. 2g).

With a phase jump in the transmission, the phase of the carrier frequency smoothly changes, and the time intervals between the pulses at the output of differentiation unit 2 change accordingly. The oscillations at the output of the block 12 for selecting the phase margin before the new installation will remain unchanged.

At the outputs of the elements And 3 and 5 (Figs. 2, 3), there will appear a packet of pulses, the beginning of which coincides with the moment of the phase change of this dressing with respect to the amount exceeding the phase margin.

At the output of the element 3 (Fig. 2z), the input of which is connected to the output of the block 12 with the zone of the minimum phase reserve, with a phase jump at the transmission pulse packets will be allocated, and on the additional elements of And 5 the pulse packets will, depending on whether Is this phase jump on the transmission the level of the phase margin determined by the corresponding output of block 12. At the maximum phase jump on the transmission, the packets of pulses are in Tc on all And 3 and 5c elements. Since the phase of the carrier oscillation changes smoothly, at first these pulses appear on the element IZ, respectively. the minimum phase reserve then on the element 5, corresponding to the phase value following in value, and last of all on the element 5, connected to the output of block 12, corresponding to the zone of maximum phase reserve.

The assignment of additional blocks 10 at the prohibition is similar to the purpose of block 8 prohibition - to select only the first impulse from the pulse packet arriving at the circuit input (fig.2k, l).

The true ZMV will be the impulse, according to that block of prohibition, the threshold

whose phase margin is half the phase jump on the gear. Pulses from the outputs of all blocks 8 and 10 of the ban are combined on the element OR

0 5

About Q

about

five

11 (fig.2m) in a single stream, and the impulse corresponding to the ETS of the true MEL will be the last.

Thus, regardless of the magnitude and sign of the phase jump on the transmission, each last pulse at the output of the STI element 11 will correspond to the true EFF. Therefore, it is necessary to pick up these pulses. This task is performed by block 13 of the discrete delay with the prohibition.

The basis of the discrete delay block-out unit 13 is a counter with a reset, the clock input of which is connected to the second output of the driver 7, and the setup input to the output of the OR 11 element. The counter is reset to each pulse generated at its installation input. The delay of the counter, determined by the division factor, is equal to half the duration of the elementary parcel, since in this zone the phase buildup process is completed, the frequency divider 6 and the phase margin selector 12 are reset, and there are no pulses at the output of the OR element 11.

Since the counter will be reset to the initial state by every impulse received from unit 12, it will count to the final state only after the last impulse in the given batch (transfer of the last impulse in the batch to a time equal to the half of the sprinkling). Further, in the delay unit, the pulse is released and delayed by half the duration of the elementary parcel, after which it acquires the desired temporary position.

Thus, the pulses at the output of block 13 of the discrete delay (Fig. 2n) are delayed with respect to the pulses at the input of this block that caused them to appear for the duration of the elementary parcel. These pulses are exactly dead in the MIT at any phase jump of the multiple phase modulation. Next, they arrive at the input of block 9 PLL

At the same time, at one output, which is the clock input of the device, the jitter of the output cycles of the device is reduced, and at the other output, the pulse of the middle of the elementary parcel, which

51343558

controls the operation of sampling block 4 and prohibition blocks 8 and lOj (fig. 2d). As a result, the stability of the autocorrelation receiver is increased.

5 f

More clearly, the operation of the device for the case of DOFM is visible from the time diagrams given. From the diagrams (Fig „2m) it is clear how much more accurately the MWH is relative to the MMM (equality of time intervals) with a phase jump of 135 ° (225 °) in the proposed device (second pulse in the right part, fig 2m) with respect to the known device (first impulse in the right part, figm) o

Claims (1)

Invention Formula A device for extracting a clock oscillation in an autocorrelation receiver, comprising a series-connected limiting amplifier, whose input is an information input M} differentiation unit, an And element and a prohibition unit, the second input of which is connected to the output of a phase-locked loop (PLL) and mouth - the new input of the sampling unit, the information input of which is connected to the output of the differentiation unit, serially connected shaper of high-frequency stabilizing oscillations and divider frequency Ota, O tl and h-35 L frequencies are informational. Yu. Now that, in order to reduce the jitter of the output cycles, the K-additional elements of the AND elements are introduced, 0 five 0 where K - - 1, a and the number of phase positions of the multiple phase modulation, to the combined first inputs of which the output of the differentiation unit is connected, To the additional inhibiting blocks, to the combined first inputs of which the output of the PLL is connected, to the second inputs to the outputs of the corresponding To additional elements And, the block selection of the phase margin, the information inputs of which are connected to the first outputs of the frequency divider, the installation input of the block selection 5 phase margin combined with the installation input of the frequency divider, connect It is gated to the output of the sampling block and is gated to the output of the device for extracting clock oscillations in the autocorrelation receiver, and all the taps, are connected respectively to the second inputs of the AND element and the K-additional elements AND, and the OR-connected in series, the inputs of which are connected to the outputs of the prohibition block and K-additional prohibition blocks, and discrete delay with inhibition, to the clock input of which the second output of the high-frequency stabilizing oscillator is connected, and the output is connected to the control at the input of the PLL, the output of which is the clock output, and the second outputs strokes of the device for the selection of clock oscillations in the autocorrelation receiver: ke Compiled by I. Gracianska Editor P.Geershi Tehred M.Dvdyk Order 4837/57 Edition 638 Subscription VNIIPI USSR State Committee for inventions and discoveries 1.13035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 0us.2 Proofreader M, Pojo