SU1553963A1 - Secondary power supply system - Google Patents

Abstract

The invention relates to electrical engineering, in particular to secondary power supply systems. The aim of the invention is to ensure the stability of operation at low load currents down to zero while maintaining a high efficiency value. The secondary power supply system provides for stabilization of the output voltage at idle or heavy underload by automatically connecting a load resistor 3 to the output terminals. The load current of the entire system is estimated from the output signals of the indication of the limiting load currents of individual voltage converters 1 without a special current sensor using indicators 4 and 5. Discrete signal processing of the status of converters 1 allows to obtain high system efficiency. 2 hp f-ly, 5 ill.

Description

01

ate

with

WITH

about

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The invention relates to electrical engineering, in particular, to secondary power supply systems (BEP).

The aim of the invention is to ensure the stability of operation at low load currents down to zero while maintaining a high efficiency value.

FIG. 1 is a block diagram of a secondary power system; FIGS. 2 and 3 are diagrams illustrating the operation of the system in FIG. 4 is a diagram of the indicator of underloading of all converters; in fig. 5 diagram of the indicator full load more than one converter.

BEP contains p parallel connected stabilized converters 1 voltage with limiting load currents connected between input and output pins, load resistor 3 is connected to output pins 2, indicator 4 inputs 4 underload of all converters and indicator full inputs 5 full load more than one converter are connected respectively to the outputs of the indication of the limiting load currents n of the voltage converters 1, and the outputs of the indicators 4 and 5 are connected respectively to the first and second y inputs of the flip-flop 6, the output of which is connected to a control input of switch 2.

FIG. 2 shows the dependence of the total current of the converters 1 voltage load current I

etc

from great

n "gr taking into account the switched current load I

UNDER

The value of 1LODr is chosen less than the max.

maximum permissible value of the load current of one converter 1pr.

SVED works as follows.

With a load current IHe, rp equal to zero, all voltage converters indicate the absence of full load. Underload indicator 4 of all converters generates a signal that sets trigger 6 to the state where key 2 is held open and therefore the load resistor is connected to output system pins. Wherein

Inverter 1 will be loaded approximately by 1/10 1P (MGy If the load current is I

n

 I

And "P

 one

H,

etc

-1 / p PoAgr), go total

(where I

load current of converters 1

yarn inp Inp + n-1 / n 1pGy.

In this case, the load current of each voltage converter 2 separately is less than Ipr.

The load indicator 4 of all converters continues to generate a trigger setup signal 6 in a state where the key 2 is held open and the load resistor 3 remains connected to the output terminals of the system.

With increasing load current in

Q 5

I limits

 1 „p-1 / p

MI

  nygr NZ

(where I

 2 (I

HI

UNDER Gr D 4J-Pr

-1 / n 1plg) the total load current of voltage converters 1 is greater than 1П1, I

podgr

but

0

five

load current I

®

45. Jq

less than 2ln + n-2 / n 1POLG. In this case, one of the converters 1, the output voltage of which is slightly higher than the output voltages of other converters due to the spread of the output nominal, takes the maximum permissible load current and indicates a full load. At that, neither indicator 4 underload of all converters, nor indicator 5 full loading more than one converter does not generate trigger setup signals 6, so the latter retains its previous state. So, if trigger 6 held key 2 open, then

 The 1 m rG 1H3 trigger 6 also holds the key 2 open and the load resistor 3 remains connected to the output terminals of the system. i

With an increase in the load current up to 1Nag-Iw, the total load current of the voltage converters 1 is 21 pr + n-2 / n 1p "dgr. At the same time, two of the inverters 1, the output voltages of which are slightly higher than the output voltages of other converters due to the variation of the output rating, take on the maximum allowable current

Voltage converters 1 provide a full load indication. They are loaded with a load current In0ftrp (Fig. 2) sufficient to ensure the stabilization of the output voltage of the system. Each stabilization of the indicator of full load indicator 5 more than one transducer appears a signal that sets the trigger 6 in the opposite state

during a full load indicator 5 more than one converter, a signal appears that sets trigger 6 to the opposite state,

515539636

whereby the key 2 is kept at the permissible load current, is uncovered. In this case, the resistor 3 will be disconnected from the output terminals of the system and the total load current of the voltage converters 1 will be reduced by the amount of the load current 1 pgr and becomes equal to ИНз 2 (1пр- - 1 / п 1пвдгр). At the same time, at the output of indicator 5 of the full load of one converter, the signal for setting the trigger 6 disappears. However, the trigger 6 continues to maintain its state

ten

During indicator 4, the underload of all converters disappears the trigger setup signal 6. However, trigger 6 continues to maintain its initial state, in which the key 2 is held open and the load resistor 3 is connected to the output terminals of the system.

With a further decrease in the system load current, the total load current of the 1 X I converters is greater than the load current of the IWarp system by

With a further decrease in the system load current, the total load current of the 1 X I converters is greater than the load current of the IWarp system by

in which the key 2 is kept closed, and the load resistor 3 disconnects the current P ° of DOWNLOAD 1 subgr, the trigger 6 starts from the output terminals of the system. is in the initial state, with coP. with a further increase in the torus current, the key 2 is closed and the load resistor 3 is the total load current of the converters 1 of the voltage Zlnpraven

1H, trigger 6 is in such a state that the key 2 is closed, the load resistor 3 is disconnected from the output terminals of the system. When the load current IMQrp IH4 (where G + n-2 / n I

H4 21Pr +

podgr at the output of the indicator 25 5 full load more than one pre-load connected to the output pins of the system.

20 In FIG. 3, where the diagrams of voltages and currents at the nodal points of the circuit are taken, the following notation is accepted: a - load current 1 ng b - total current of converters l вp j c - voltage on the 2 U key of the cursor again a signal appears, however it is not affected em on trigger state 6.

When the load current changes in the opposite direction (decrease of the system load current) from the nominal value to 1Hgr 1H4 at the output of the full load indicator 5 more than one converter, the trigger setup signal 6 disappears. However, the trigger 6 also continues to maintain its state. In this case, the key 2 is kept closed, and the load resistor 3 is disconnected from the output terminals of the system.

ca 2, g output voltage

U 8OX FIG. 4 shows an example of the implementation of the indicator 4 underloading of all converters in the form of a 7-input match element, and indicator 5 full load of more than one converter in the form of serially connected 7-input adder of single-charge binary numbers and a digital comparator with a threshold of one.

When reducing the load current of the system to less than 1Ng, none of

current 1pr, so all voltage converters 1 indicate the absence of

Here is the log. O at the input corresponds to the underloaded state, and 40 log about 1 to the state of limiting the load current of the converter 1.

The 7-input match element is made on two elements 4 OR-NOT and

voltage converters 1 will not be one 2I. State log. 1 is loaded at the maximum allowable course of the indicator 4 is possible only in

 In the event that all the indication signals of limiting the load currents of prefull loading. In this case, at the output of indicator 4 of underloading of all converters, a signal is generated that at 50 ° DIN of seven indication signals, the limiter returns trigger 6 to the initial conversion load current, in which the key 2 of the voltage opener 1 is a log 1, and the load resistor 3 is connected to the output of the indicator 4 will be a log. Oh, to the output pins of the system. The sum-7-input adder of one-digit sampling current load of converters of binary numbers is made on two full-voltage IrtA increases in single-digit intermittent totalizers 2TI / L4 com by the value of the load current IpoArf. and one two-bit adder 5 3; At the same time, one of the converters 1 Indicator 5 operates as follows takes over as many times as possible.

Formative voltage is in the state log. O. If at least

During indicator 4, the underload of all converters disappears the trigger setup signal 6. However, trigger 6 continues to maintain its initial state, in which the key 2 is held open and the load resistor 3 is connected to the output terminals of the system.

With a further decrease in the system load current, the total load current of the 1 X I converters is greater than the load current of the IWarp system by

s of current P ° of LOADING 1 podgr, trigger 6 is in the initial state, in which the key 2 is closed and the resistor 3

podgruzki connected to the output pins of the system.

FIG. 3, where diagrams of voltages and currents are shown at node points of the circuit, the following notation is accepted: a - load current 1 nag b - total current of converters lЈp j c - voltage on key 2 U key 2, g voltage on output pins

U 8OX FIG. 4 shows an example of the implementation of the indicator 4 underloading of all converters in the form of a 7-input match element, and indicator 5 full load of more than one converter in the form of successively connected 7-input adder of one-charge binary numbers and a digital comparator with a threshold of one.

In the event that all indication signals of limiting the load currents of the predin DIN and seven signals of the indication of the limitation of the load currents of the voltage converters 1 are log 1 at the output of indicator 4 there will be a log. About the 7-input adder of single-digit binary numbers is made on two full single-digit adders 2RTI / L4 and one two-digit adder5 3, Indicator 5 works as follows.

Formative voltage is in the state log. O. If at least

The inputs of each one-bit full adder 2L 1 and 5 (Fig. 4) are supplied with three indication signals of load current limitation from the voltage converters 1. At the outputs of these adders, two 2-bit binary numbers are obtained, and S2.jS17. Further, these numbers are added to the two-bit adder with the seventh signal indicating the indication of the limiting load current of the seventh voltage converter 1. At the output of the adder, we obtain a 3-bit binary number S33S23Slj, representing the number of fully-loaded current transformers t. For example, with one (any) loaded converter, the code 001 is present at the output of the adder, with three -011, with five 101, and so on.

This code is fed to the inputs of the first number (A) of a digital comparator chip. At the inputs of the second number (B), the code 001 is continuously supplied. In this turn on, the digital comparator chip compares the number A with the number 001 and determines the sign of the inequality causing the signal log. 1 at the corresponding output at A B. Since B 001, and the number A is equal to the number of fully-loaded converters 1, then at the output of the digital comparator log. 1 appears if the number of fully current-loaded converters 1 is greater than One, i.e. this output is the output of indicator 5.

FIG. Figure 5 shows the make-up artist of the implementation of the indicator 4 underloading of all converters and indicator 5 full load of more than one converter in the form of serially connected n-input adder IE of one-digit binary numbers and a DS decoder with two outputs (). The structure, operation and output signals of the adder are described above with reference to the circuit of FIG. four.

In the diagram of FIG. 5, the binary number S3S2S1, which represents the number of current converters 1, is loaded from the output of the adder to the outputs of the DS decoder, performed, in particular, on elements 3 OR-NOT and 2 OR.

Here is the log. 1 at the output of indicator 4 appears only if the binary number S3S2S1 is 0000 (i.e., the number is completely

„)

5 5 0

0

0

five

current converters 1 equals zero).

If at least one of the bits of the binary number S3S2S1 is equal to 1, then during indicator 4 you will see a log. ABOUT.

The inputs of the logic element 2 OR are connected to the outputs of the higher bits S3 and S2 of the adder Q.

When the number of fully-loaded converters 1 is zero or one, the values of both bits S3 and S2 of the binary number S3S2S1 are equal to 0. If there are more fully-loaded converters 1 by at least one of the bits S2 or S3, then the log „1 and, therefore, s at the output of indicator 5 will also be log 1.

Thus, the proposed secondary power supply system provides for stabilization of the output voltage at idle or strong underloading by automatically connecting the load resistor 3 to the output viewpoints.

High efficiency in the SVEP is provided by discrete processing of the signals of the state of stabilized voltage converters 1, which makes it possible to estimate the magnitude of the load current of the system without a total current resistance sensor on which additional power is lost.

Claims (3)

Invention Formula one . A secondary power supply system containing p parallel-connected stabilized voltage converters with limited load currents connected between the input and output pins, characterized in that, in order to ensure: stability of operation at low: load currents down to zero, an underload indicator is introduced all converters, a full load indicator for more than one converter, a trigger and a chain consisting of a load resistor and a switch connected in series. connected to the output pins, with n inputs of the underload indicator of all converters and n inputs of the full load indicator of more than one converter connected respectively to the outputs of the indication of the load current n converters 1553 voltage inputs, and the outputs of the underload indicator of all converters and the full load indicator of more than one converter are connected respectively to the first and second inputs of the trigger, the output of which is connected to the control input of the key. 2. The system under item 1, about tl and h So that the indicator of under-JQ inputs of the adder are the inputs of all converters made in the form of an n-input matching element, and the indicator of full load of more than one converter is made in the form of serially connected 15 n-input adders of single-digit binary numbers and digital comparator with a threshold unit. Dicators, the first output of the decoder of binary numbers smaller than one is used as the output of the underload indicator of all converters, and the second output of the decoder of binary numbers greater than one is used as the output of the full load indicator of more than one converter. 3 ten 3. The system of claim 1, wherein the underload indicator of all converters and the full load indicator of more than one converter are made in the form of serially connected n-input adder of single-digit binary numbers and a decoder with two outputs, Dicators, the first output of the decoder of binary numbers smaller than one is used as the output of the underload indicator of all converters, and the second output of the decoder of binary numbers greater than one is used as the output of the full load indicator of more than one converter. Limit indication tm-ruzhochnil / sho9 & & weofytaofame- o | - lei tension o4- rtJL Compiled by A. Volkov Editor L. Veselovska Tehred A. Kravchuk Order 456 Circulation 652 VNSHPI State Committee for Inventions and Discoveries at the State Committee for Science and Technology of the USSR 113035, Moscow, JK-35, Raushsk nab. 4/5 0 vshod about indu & ztor & 5 Proofreader M.Kucher va Subscription