CA1077624A - Gain method and apparatus for a delta modulator - Google Patents

Abstract

GAIN METHOD AND APPARATUS
FOR A DELTA MODULATOR

Abstract of the Disclosure In a delta modulator a sequence of code symbols are generated which are indicative of increments of signal level, with each code symbol being determined in accordance with the difference in signal level between an input signal and a prediction signal which is a representation of the input signal. A sequence of the generated code symbols are stored, including the most recent code symbol and a preceding number of code symbols, with the pattern or code symbols at any instant defining a state of signal activity.
There is a table of delta increments, a table of threshold values, and a digital gain logic network, all of which provide signal outputs which are controlled by the state of signal activity represented by the stored code signal pattern. The signal output from the delta table and the threshold table are modified an amount determined by the value of the signal output from the digital gain logic network. An accumulation of modified delta increments are summed with modified threshold values for providing the prediction signal. The prediction signal and the input signal are compared for generating a new code symbol.

Description

~ackgrourld of the Invention 26 Many linear or fixed step size delta modulators 27 experience difficulty in following sudden varlaticns in 28 input si~nal amplitude. ~henever an abrupt trans tion . ~ . . .
~ . .
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1~7624 1 from one amplitude to a much different amplitude occurs,

2 it takes a given length of time for the differential

3 encoding process to integrate to a corresponding change

4 in the encoded representation of the signal. This condition is known technically as "slope overload", and arises from 6 the fact that in conventional delta modulators, t'here are 7 certain practical limitations upon the size of the 8 increments by which the amplitude of the reconstructed 9 waveform is changed from one sample time to the next.
If the increment is made small, the modulator responds 11 slowly to steep transitions in the amplitude of the input 12 signal waveform, thereby introducing phase shifts and other 13 distortions into the reconstructed signal waveform. On 14 the other hand, if the increment is made large enough so that the encoding process immediately starts to follow 16 a very steep and prolonged transition of the input signal 17 amplitude, then, with the same large increment~ the system 18 becomes unstable and shows a tendency to overshoot and 19 oscillate when the transition peak is reaclled. Also, an undesirable amount of granular noise may be generated 21 during intervals when the input signal amplitude is constant 22 or only slightly varying. Certain delta modulators, ~Ihich 23 are called adaptive delta modulators, provide ~ differential 24 encoding increment of adjustable size which is small at times when the system is idling and larger at times when 26 the signal amplitude is varying rapidly. In some prior 27 art delta modulators there is a fixed threshold value to 28 which the delta increments are compared for determining 29 the amount the new prediction signal is changed, while in other delta modulators the threshold value is a state . . . -1~77624 1 dependent value, as is a delta increment. In the latter 2 type delta modulator, a new threshold value is chosen at 3 each sample time, as is the delta increment. One such 4 delta modulator is disclosed in U.S. Patent 3,628,148 issued in the name of Steven J. Brolin. In the Brolin 6 patent the number of available delta increments ànd the 7 number of available threshold values are determined by 8 the number of stages in the input storage register in which 9 the respective code symbols are stored. To increase the number of available delta increments and available threshold 11 values, the number of stages in the storage register must 12 be increased and accordin~ly the size of the delta increment 13 table and threshold table must be increased. In such a 14 system, to have available an optimal number of threshold values and delta increments, the number of circuits and 16 logic elements increase accordingly, resulting in an 17 increase in the cost and size of the delta modulator.
18 Accordin~ to the present invention, a delta 19 modulator is disclosed which also utilizes a table of threshold values as well as a table of delta increments, 21 which respond to stored code symbols for selecting threshold 22 values and delta increments. An optimal number of delta 23 increments and threshold values are available, not by 24 utilizing more storage stages and larger tables, but rather by using a modifying network which consists of an integer 26 arithmetic digital gain logic circuit which also responds 27 to the stored code symbols for providing a modifying signal 28 which modifies the selected delta increment and the selected 29 threshold value, thereby in effect increasing the effective 76~4 1 size of the respective tables, while minimizing the increase 2 in circuits and logic elements and accordingly the attendant 3 cost of such elements.

4 Summary of the Invention According to the present invention, a delta 6 modulator is disclosed which includes method and apparatus 7 for generating code symbols representing increments of 8 signal level, ~ith each code symbol being determined in 9 accordance with the difference in signal level between an input signal and a prediction signal which is a 11 representation of the input signal, with the prediction 12 signal being formed by accumulation of successive signal 13 level increments which depend on the history of the code -14 symbols. '~here is means for storing a sequence of generated code symbols, the sequence including the most recent code 16 symbol and a given number of preceding code symbols, with 17 the pattern of code symbols at any instant defining a state 18 of signal activity. There is also means for producing 19 three signals in accordance with the state of signal activity represented by the stored code symbol pattern, 21 namely an incremental signal level, a threshold value and 22 a modifier signal. Also inoluded is means for modifying 23 the incremental signal level and the threshold value an 24 amount determined by the modifier signal. Finally, there is means for forming a new prediction signal by aGcumulation ~6 of successive modified signal level increments which are 27 summed wi~h successive modified threshold values, including 28 means for generating a new code symbol in response to 29 comparing the new prediction signal ~lith the input signal.

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~: ' 1~:)77624 1 Brief Description of the Drawings FIG. 1 is a block diagram representation of the encoder section of the delta modulator according to the present invention.
FIG. 2 is a timing diagram which is useful in understanding the operation of the encoder set forth in FIG. 1 and FIG. 5.
FIG. 3 is a block diagram representation of the decoder section of the delta modulator according to the present invention.
FIG. 4 on the sheet of drawings bearing Fig. 2 is a timing diagram helpful in the understanding of the decoder illustrated in FIG. 3 and FIG. 14.
FIGS. 5A, 5B, 5C and 5D, taken together as shown in FIG. 5, illustrate a more detailed showing of the encoder section of the delta modu-lator according to the present invention.
FIGS. 6A and 6B taken together as shown in FIG. 6 is a block diagram representation of the delta value table illustrated in FIG. 5C.
FIGS. 7A and 7B taken together as shown in FIG. 7 is a block diagram representation of the threshold table illustrated in FIG. 5D.
FIGS. 8A and 8B taken together as shown in FIG. 8 is a block diagram representation of gating network 120 illustrated in FIGS. 5C and 5D.
FIGS. 9A and 9B taken together as shown in FIG. 9 is a block diagram representation of gating network 122 illustrated in FIGS. 5C and 5D.

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1~776Z4 1 FIG.S. lOA and lOB taken together as shown in ~IG.
2 10 is a block diagram representation of gating network 3 124 illustrated in ~IGS. 5C and 5D.
4 FIGS. llA and llB taken together as shown in FIG.
11 is a block diagram representation of gating network 6 126 illustrated in FIGS. 5C and 5D.
7 FIGS. 12A and 12B taken together as shown in FIG.
8 12 is a block diagram representation of gating network 9 128 illustrated in FIGS. 5C and 5D.
FIGS. 13A and 13B taken together as shown in FIG.
11 13 is a diagram of gating network 130 illustrated in FIGS.
12 5C and 5D.
13 FIGS. 14A, 14B, 14C and 14D taken together as 14 shown in FIG. 14 is a more detailed block diagram representation of the decoder section of the delta modulator 16 according to the present invention.
l? FIGS. 15A, 15B, 15C, 15D, 15E, 15F, 15G and 15H
18 taken together as shown in FIG. 15 is a block diagram 19 representation of the filter value table illustrated in FIG. 14C.

22 Description of the Preferred Embodlment 23 The delta modulator according to the present 24 invention is set forth in digital hardware form, it is to be appreciated however that the present invention may 26 be practiced through the use of a properly program~ed 27 general purpose digital computer, or by other suitable 28 techniques.
29 In FIG. 1, an encoder for the delta modulator is illustrated generally at 2. A comparator 4 receives 10'776Z~

1 an analog input from an analog source 6, and a prediction 2 sisnal, which is a representation of what it is anticipated 3 the input signal is to look like from one sample time to 4 the next, from a D/A converter 8. For description purposes only, it is assumed that the analog input signal is an 6 audio signal. However, those skilled in the art will 7 appreciate that other signals such as video signals, for 8 example, may be used in the practice of the present 9 invention. The output signal from the comparator 4 on an output line 10 is a code symbol which has a first binary ll value, for example a binary l, when the signal appearing 12 on the analog input signal line is greater than or equal 13 to the value of the prediction signal appearing on the 14 other input line. Conversely, if the analog input signal has a level which is less than the prediction signal, a 16 code symbol signal indicative of a binary 0 value appears 17 on the output li~e 10. In practice, the code symbol from 18 the comparator 4 appearing on the line lO may be represented 19 by a pulse or no-pulse condition, a positive pulse or negative pulse condition; or by a double rail type system 21 wherein there is a first output line and a second output 22 line from the comparator, with a pulse being present on 23 the first output line when there is a binary l condition 2~ sensed by the comparator 4, and conversely there being a pulse output on the second output line when there is 26 a binary 0 condition sensed by the comparator 4. A gate 27 12 passes the appropriate binary l or 0 code symb~l 28 indication to an output line 14, with this signal being 29 provided to an output terminal 16 and to the input of a shift register such as the storage register 18. The code - : :...... , -, . : :
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1 symbol si~nal indication appearing at the terminal 16 is 2 provided to an output line 20 and from there to delta 3 modulator decoder apparatus which is illustrated in FIG.
4 3.
The storage register 18 includes a predetermined 6 number of stages and, by way of example only, the storage 7 register is chosen to have four stages, with the stored 8 binary bit pattern at any instant defining a state of 9 signal activity relative to the input signal. ~he output 10 from the storage register 18 is applied in parallel to r 11 a decoder apparatus 22 which decodes the message stored 12 in the storage register 18 and provides on one of sixteen 13 output lines shown at 24, a signal indicative of the present 14 state of signal activity. The output of the decoder 22 ' 15 is provided on the line 24 to the respective inputs of 16 a delta table 26, a gain logic network 28, and a threshold - -17 table 30.
18 The delta table 26 is a table look-up device such l9 as a read-only memory in which there are stored 16 integer 20 values which may be positive or negative numbers in 2's 21 complement form and ~7hicll values are addressed by the 22 output of the decoder 22. At any given sample time one 23 of the values is selected in response to the decoded message 24 and applied to the input of a plurality of gates which 25 is illustrated generally at 32. As is known in the art, 26 the delta increments selected from the table 26 are 27 accumulated and form in part the prediction signal which 28 is applied to the input of the comparator 4. This is to 29 be described in more detail shortly.

YO973-005 -~- -: , .
. ' : , ' .. ' . ' : ' . . ' 1~776Z4 1 The tilreshold table 30 is another look-up ~cvice 2 containing 16 integer values which may be positive or 3 negative numhers in 2's complement form and which are 4 addressed by the decoder 22, with the selected integer value output from the table 30 heing applied to the input 6 of a plurality of gates ~hich are illustrated generally 7 at 34. The integer value output from the threshold table 8 30 is subsequently used as a threshold or reference level 9 to which the successive accumulated delta increments are added for forming the prediction signal.
11 The gain logic networ~ 28 is comprised of an 8-12 bit counter and two decoder networks, the function of which 13 is describe~ relative to FIG. 5D. The gain logic network 14 28 responds to the decoded message from the decoder 22 and in response thereto provides a modifier signal on an 16 output line 36 which is used to modify the selected delta 17 increment and the selected threshold value. This mo~ifier 18 signal may be, for example, a multiplier signal which 19 multiplies the selected delta increment value and the selected threshold value by an integer amount dependent 21 upon the state of signal activity represented by the output 22 of the decoder 22. In the embodiment set forth, the integer 23 values used in the multiplication process may be 1, 2, 24 4, 8, 16, or 32. The gain logic netwoxk 28, therefore, functions to expand the available values from the tables 26 26 and 30 while minimizing the numher of required logic 27` networks and space required in the encoding device.
28 The respective outputs from the gates 32 and 34 29 are applied, at selected time intervals, via line 38 to the input of a data registex 40, with the data register YO973-005 _9_ 1~776Z4 1 at one time period storing the modified delta increment, 2 and at another time period, storing the modified threshold 3 value. The timing sequence provided by the pulse generator 4 5 is described shortly. The output from the data register 40 is applied via a line 42 to the first input of an adder 6 44, with the output of the adder 44 being applied via a 7 line 46 to respective first inputs of a gate 48 and a gate 8 50. The gate 50 provides on an output line 52 the -9 respective summed modified delta increments which are applied to the input of an accumulator 54, with the 11 accumulated modified delta increments being applied via 12 an output line 56 to the input of a gate network 58, with 13 the gate 58 passing the accumulated modified delta 14 increments to the input of a data register 60 which applies the accumulated modified delta increments to a second input 16 of the adder 44 via a line 62. It is seen that the adder 17 44, therefore, sums the previous accumulated~modified delta 18 increments with the new modified delta increment and the 19 new modified threshold value. The gate ~8 passes the successive modified delta signal level increments which 21 have been summed with the successive modified threshold 22 values and applies this digital signal via a line 64 to 23 an input of a shift register 66 which applies this signal 24 via a line 68 to the input of a D/A converter 8 for providing the analog prediction signal, which is a 26 representation of the input signal, to the second input 27 of the comparator 4 for comparison with the input signal.
28 Refer now to FIG. 2 which is a timing diagram 29 which sets forth the timing sequence for the encoder 2 illustrated in FIG. 1. For system initialization conditions - - -:

~ .
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1~776Z4 1 assume that the gain logic network 28 provides a signal 2 output calling for maximum multiplication of the delta 3 increment and the threshold increment, namely a value of 4 32. Also, assume that the accumulator 54 has stored therein the maximum negative numher. The maximum gain from the 6 network 28 and the maximum accumulated negative number 7 from the accumulator 54 is chosen such that the encoder 8 2 rapidly integrates towards the value of the input signal, 9 since the level of the prediction signal initially lags the level of the input sign~l. At pulse Pl time, the shift 11 register 18 is pulsed to shift the presently stored message 12 into the temporary storage stages. At this time the message 13 stored is all zeros, 0 0 0 0. The gates 34 also are sampled 14 for determining the amount the present threshold value is to be multiplied. When there is a state of signal 16 activity represented by all zeros, the gain logic networ~.
17 is incremented by a count of 8, as will be described in 18 more detail shortly, and accordingly the selected threshold 19 value which at this time is -34 tFIG. 7A, register 340), is multiplied by the factor 32 and applied to the input 21 of the data register 40 and from there to the input of 22 the adder 44. This signal is then added,wi~h the present 23 accumulated sum from the accumulator 54 and the new signal 24 appearing on the output line 46 is the old accumulation plus the modified threshold value which is passed hy the 26 gate 48 at pulse P2 time to the data register 66 and to 27 the D/~ converter 8 for forming the new analog prediction 28 signal which is applied to the second input of the 29 comparator 4 for providing a new code symbol, namely a binary 1 signal output on the line 10 to the input of the - , -: . - ~

1~77~24 1 gate 12. It is assumed that the signal is a ~inary 1 level 2 since it takes a finite amount of time for the level of 3 the prediction signal to catch up with the level of the 4 input signal. ~t time P3 the gate 12 is sampled and the binary 1 code symbol signal indication is manifested on 6 the output line 14, is applied to the terminal 16 and in 7 turn to the input of the storage register 18, with this 8 signal being stored in the first stage of the shift register 9 at P3 sample time. At pulse P4 time, the gain logic networ~
28 responds to the decoded message from the decoder 22 11 and in response thereto the 8-bit counter is decremented 12 by 2, due to the binary condition 0 0 0 1 as is explained 13 in more detail shortly, and the resultant new modifier 14 signal is applied to the gates 32 and 34, respectively.
At pulse P5 time, the gate 32 has the selected delta 16 increment multiplied by the multiplication factor from 17 the gain logic network 54 and this modified delta increment :
18 signal is applied to the data register 40 and in turn to 19 the first input of the adder 44 for addition with the previous accumulated modified delta increments. ~t P6 21 time the output of the adder 44, which is the sum of the 22 accumulated modified delta increments and the new modified 23 delta incxement, is passed to the input of the accumulator 24 54 by way of gate 50. It is to be noted at this time that the accumulated modified delta increments are passed to 26 the accumulator 54 rather than being passed by the gate !
27 48 to the data register 66 and the D/A converter 88. This 28 is so since the accumulated modified delta increments are 29 summed with the selected modified threshold value prior to being converted to the prediction signal. It is seen, .

:

1(1 776Z4 1 therefore, that the modified delta incremcnts are 2 accumulated, and therefore are cumulative in nature, whereas 3 the selectecl modified threshold values are not accumulated, 4 but are used as a reference value from one sample time to the next. The operations performed by the adder and 6 accumulator are all done by 2's complement arithmetic.
7 The cycle just described keeps repeating for the duration 8 of system operation.
9 Refer now to FIG. 3 which is a block diagram representation of the decoder portion of the delta 11 modulator, and which decoder is illustrated generally at 12 70. The generated code symbols from the encoder 2 as 13 manifested on the line 20 are provided to the respective 14 inputs of a shift register such as the storage register 72, and a pulse generator 74, which provides timing for 16 the decoder in synchronization with the received code 17 symbols. The storage register 72 is, for purposes of 18 illustration only, illustrated as a 6-stage shift register, 19 with the sequence of stored code symbols including the most recent code symbol generated and the preceding five 21 code symbols. The pattern of stored code symbols, at any 22 instant, defines a state of signal activity relative to 23 the received signal. The output of all 6 stages are 24 provided to a first decoder 76, with the outputs of the second through fifth stages being provided to a decoder 26 7~, and with the outputs of the third through sixth stages 27 being provided to the inputs of a decoder 80. The decoded 28 message from the decoder 76 is provided to the input of 29 a filter table 82 which functions to provide a non-linear smoothing value for the received code symbols. The filter 1~3776Z~

1 table is described in detail in copending Canadian patent application serial number 221,462 filed March 5, 1975, on behalf of P.A. Franaszek et al, which patent application is assigned to the assignee of the present invention. The output from the decoder 80 is provided to the input of a delta table 84 which is identical in operation to the delta table 26 illustrated in FIG. 1. The output from the decoder 78 is provided to the input of a gain logic network 86 wh;ch is similar to and functions in a like manner as the gain logic net-work 28 illustrated in FIG. 1. The selected smoothing value from the filter table 82 is provided to a plurality of gates 87 which are under the control of the gain logic network 86 to provide a modified smoothing value which is the selected smoothing value multiplied by a predetermined integer value as de~er-mined by the gain logic network 86.
The signal output from the delta table 84, that is the selected ; incremental signal level, is passed to the gates 88 which provide a modified ~ -incremental signal level output which is the selected incremental signal::
multiplied by an integer value determined by the gain logic network 86. The respective outputs from the gates 87 and 88 are provided at selected times via a line 90 to the input of a data register 91 which in turn provides an output signal to the first input of an adder network 92, which output signal is summed with successive accumulated modified signal increment levels. The output of the adder 92 is provided to the input of a gate 93, the input of a gate 94, and the input of a gate 95. The signal passed by the gate 93 is the accumulated modified delta increment .

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1 values which have been summed with successive modified 2 smoothing values from the filter table 82. This signal 3 is then passed to the input of a data register 96, and 4 then to a D/A converter 97, with the analog signal appearing at the output thereof being provided to an analog receiver 6 98 as a usable reproduction of the analog input signal 7 provided by the source 6 as shown in FIG. 1.
8 The output from the adder 92 is passed by the 9 gate 95 to the accumulator 99 for accumulation of the modified delta increments, which are then passed by a gate 11 100 to the input of data register 101, which also has 12 applied to the same input, via the gate 94, non-accumulated 13 modified delta increments. The modified delta increment 14 values appearing at the output of the shift register 101 are provided to a second input of the adder 92 and are 16 summed with the new modified smoothing value.
17 Refer now to FIG. 4 which is a timing diagram 18 which sets forth the timing sequence of the decoder 70 19 illustrated in FIG. 3 and 14. At ~1 pulse time the code symbols stored in the storage register 72 are shifted to 21 the temporary storage portion thereof. ~t pulse Q2 time 22 the code symbols stored in the temporary stages of the 23 register are then shifted to the following stages and the 24 accumulated modified delta increments are shifted from the accumulator 99 through the gate 100 and the data ' 26 register 101 to the adder 92 for addition with the modified 27 smoothing value. At pulse Q3 time the decoder 78 is sampled 28 by the gain logic networ~: 86 for determining which modifier 29 signal is to be generated in response to the present state of signal activity. At pulse Q4 time the selected delta 1~776Z4 1 increment, as manifested at the output of the delta table 2 84, is modified, that is multiplied, by the selected integer 3 value from the gain logic network 86 and is passed via 4 the line 90 to the input of the data register 91 and then to the adder 92 for addition with the old sum presently 6 stored in register 101. At pulse Q5 time the new sum 7 output from the adder 92 is passed by the gate 94 to the 8 input of the data register 101, and is passed by the gate 9 95 to the input of the accumulator 99. At pulse Q6 the selected smoothing value from the filter value table 82 11 is modified, that is multiplied in the gates 87 by the 12 selected integer value from the gain logic network 86 and 13 is passed by the line 90 to the input of the data register 14 91 and to the adder 92 for addition with the new sum.
At pulse Q7 time the output from the adder 92, which is 16 the new sum plus the modified smoothing value, is passed 17 by the gate 93 to the shift register 96 and from there 18 to the D/A converter 97 for conversion to analog form for 19 reception by the analog receiver 98 for reconstructing the input signal. This cycle repeats for the duration 21 of system operation. It is seen that the delta increments 22 are accumulated and are summed with successive modified 23 smoothing values for forming a digital signal which is 24 subsequently converted to analog form for reception by the analog receiver 98.
26 Refer now to ~IG. 5 and in particular to FIG.
27 SA which is a portion of the encoder 2 as illustrated in 28 FIG. 1. The encoder is shown as a double rail system, 29 that is, for each element in the system there is a ~irst line for binary 1 signals and a second line for binary yog73-ooS -16-.

10~6Z~a 1 0 si~nals. Accordingly, when there is a binary 1 signal 2 there is a signal on the first line and no signal on the 3 second line. Conversely, when there is a binary 0 signal, 4 there is a signal on the second line and no signal on the first line. That is, when the first line is active the 6 second line is inactive and vice versa. The comparator 7 4 receives at a first input the analog input signal from 8 the source 6 on line 102, and receives the prediction 9 signal at a second input via line 104 as explained relative to FIG. 1. When the analog input signal appearing on line 11 102 ls greater than or equal to the analog prediction 12 signal appearir,g on line 104, there is a signal manifested 13 on the line 106, that is line 106 is active and line 108 14 is inactive, representing a binary 1 condition. I~henever the prediction signal appearing on line 104 is greater 16 than the analog signal appearing on line 102, there is 17 a signal manifested on the line 108, that is the line 108 18 is active and line 106 is inactive, representing a binary 19 0 condition. At pulse time P3 the gate 12 passes the signal which is manifested on the particular active line 21 at this time, with the signal being applied to the storage 22 register 18, and via the line 20 to the decoder 70.
23 The storage register 18 is comprised of flip-flop 24 stages 142, 144, 146, and 148. There are intermediate storage stages comprising flip-flops 150, 152, and 154.
26 At pulse Pl time as manifested on line 156, contents of 27 flip-flop 142 are passed by a gate 143 to storage stage 28 150; the contents of flip-flop 144 are passed by a gate 29 145 to storage stage 152; and the contents of flip-flop 146 are passed by gate 147 to the storage stage 154.

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1 ~t pulse P3 time, the gate 12 ~asses the generated 2 code symbol froM the comparator 4 to the first stora~e 3 register stage 142. Also at P3 time the gate 151 is enabled 4 to pass the information stored in the flip-flop 150 to the second storage register stage 144; the gate 153 is 6 enabled to pass the information stored in the flip-flop 7 152 to the third storage register stage 146i and the gate 8 155 is enabled to pass the information stored in the flip-9 flop 154 to the fourth storage register stage 148. The decoder 22 decodes the instant sequence of code symbols 11 stored in the storage register 18, for determining the 12 instant state of signal activity, and provides on an output 13 line 24 at any instant one of the 16 possible ~ecoded 14 binary signals illustrated on the line 157, with these binary decoded signals also being manifested on the line 16 112 which connects to the delta value table 26 and the 17 threshold table 30. The 16 possible information lines 18 forming the line 157 are connected in a predetermined 19 manner as illustrated to OR gates 159, 161 and 163, with the outputs of these gates being connected to the gain 21 logic network 28 which is illustrated in FIG. 5D. The 22 gate 159 is enabled whenever there is a high state of 23 signal activity which is manifested by either a condition 24 of all 0 15, or all l's in the decoded sequence. The gate 161 is enabled whenever there is an intermediate state 26 of signal activity, such as a condition of 0 0 0 1, or 27 a condition of 1 1 1 0. The other binary states which 28 enable the gate 161 ~re readily ascertained from FIG. 5A.
29 The gate 163 is enabled whenever there is a low state of signal activity, such as 0 1 0 0 or 1 0 1 1, with other Y~973-005 -18~

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1 states of siynal activity which enable the gate 163 being 2 readily ascertainable from FIG. 5~.
3 Refer to FIG. 5B which illustrates the delta value 4 table 26 and the gates 32. The binary coded signal .appearing on line 112 energizes, at any given time, one 6 of a possible 16 output lines 114 from the delta value 7 table 26 with the output signal from table 26 being applied 8 concurrently to gates 120, 122, 124, 126, 128, and 130, g with only one of these gates being enabled at any instant of time. Appe~aring on line 36 is the multiplier signal 11 from the ~ain logic network 28 as illustrated in FIG. 5D.
12 At any given time one of the lines 181, 183, 185, 13 187, 189 and 191 is active for enabling a selected one 14 of the gates 121, 123, 125, 127, 129 and 131, respectively, for providing a signal output at pulse P5 time for modifying 16 the selected delta increment. For a low state of signal 17 activity, as represented by the decoded sequence from the 18 decoder 22, the gain logic network 28 provides an enabling 19 signal on the line 181 for permitting the gate 121 to provide a signal output at pulse P5 time for enabling the 21 gate 120 to p:rovide a modified delta increment to the line 22 38. Whenever the gate 120 is enabled, the selected delta 23 increment from the delta increment table is multiplied 24 by 1, that is the delta increment remains the same.
Whenever an enabling signal is present on the line 183 26 the gate 123 is enabled for providing a signal output for 27 enabling the gate 122 to effect multiplying the sblected 28 delta increment value by 2. Whenever the line 185 is 29 active, the gate 125 is enabled for providing a signal output for enabling the gate 124 to effect multiplying ~ : . . - - ~ . : . , -::~07~62~

1 the selected delta increment value by 4. Whenever the 2 line 187 is active, the ~ate 127 is enabled for providing 3 an output signal for enabling the gate 126 to effect 4 multiplying the selected delta increment value by 8.
Whenever the line 189 is active the gate 129 is enabled 6 for providing an output signal for enabling the gate 128 7 to effect multiplying the selected delta value increment 8 by 16. ~henever the line 191 is active, the gate 131 is g enabled for providing an output signal for enabling the gate 130 to effect multiplying the selected delta value 11 increment by 32. The functioning of the respective gates 12 in the gates 32 is described in more detail relative to 13 FIG. 6. Suffice it to say that the multiplications 14 performed by the gates 32 is by shifting techniques, that is, when the message is to be multiplied by 2, it is shifted 16 one place, and when it is to be multiplied by 4 it is 17 shifted by two places, and so on.
18 The accumulation and addition process performed 19 by the accumulator 54, adder 44 and associated gates and registers is the same as described relative to FIG. 1, 21 and accordingly the description is not repeated here.
22 Refer to FIG. 5C which illustrates the threshold 23 table 30, and the gates 34. The threshold table 30 responds 24 to the decoded message on line 112 for activating one of 16 output lines 118 which provide a selected threshold 26 value to the respective gates comprising the gates 34.
27 The gates 34 are identical to the gates 32 with like 28 elements having a prime affixed thereto, and therefore 29 their operation is not explained in detail, except that the gates 34 perform the modification operation in response . ~

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1 to the pulse Pl appearin~ on the line 184. A source of 2 logical 1 is provided at a terminal 135, and a source of 3 logical 0 is provided at a terminal 137 for providing 4 energization potential for the gates 32 and 3~. In practice, the terminals 135 and 137 are returned to a 6 source of positive potential. In practice, however, it 7 is a design choice whether to use positive potential, 8 negative potential, a positive source of current or a 9 negative source of current.
Refer to ~IG. 5D, which illustrates in detail 11 the gain logic network 28, which network selects the 12 modifier signal in response to the state of signal activity 13 represented by the decoded signal appearing on line 24 14 at the output of the decoder 22. The gain logic network 28 includes an 8-bit counter 162, which includes a low 16 order section comprised of the first five stages of the 17 counter, and a high order section which is comprised of 18 the three high order stages of the counter. There is a 19 decoder 166 which is responsive to the counts in the five low order stages of the counter, and a decoder 164 which 21 is responsive to the three high order stages of the counter.
22 The three high order stages of the counter are l 23 interconnected such that there can never be a count of 24 higher than 5 manifested by the three high order bits.
Therefore, the decoder 164 is designed to respond to the 26 counts 0 through 5, which are manifested on the decoder 27 output lines 109, 111, 113, 115, 117, and 119, respectively.
28 The decoder 166 responds to a count of 0 on a line 103, 29 a count of 1 on a line 105, and a count of greater than 24 on a line 107. The counter 162 is never allowed to ' :

:~, -- .

1~77~Z4 1 be decremented helow 0, and the count indicative of the 2 state of the three high order bits are never allowed to 3 exceed the value of 5. At pulse P4 time, as manifested 4 on line 192, one of gates 170, 174, or 180 are enabled to either increment or decrement the counter. In some 6 instances, however, the counter is neither incremented 7 or decremented, depending upon the state of signal activity 8 and the instant count in the counter. The logic for 9 assuring that the counter 162 is never decremented below zero is effected in part by the gate 171, which has inputs 11 from the lines 103 and 109 which is a zero count line from 12 the decoders 166 and 164, respectively. When both of these 13 lines are active, there is a signal output from the gate 14 171 which is passed by an inverter 168 as a negative signal which disables an AND gate 170 which prevents the counter 16 being decremented by 1. Also at this time the OR gate -17 176 passes the signal output from the yate 171 which is 18 inverted by an inverter 172 for disabling and AND gate 19 180, which prevents the counter from being decremented by 2. Whenever there is a count of 1 in the decoder 166 21 and a count of 0 detected by the decoder 16d, the lines 22 105 and 109 are active enabling the gate 179 to provide 23 a signal output which is passed by the OR gate 176 which 24 is inverted hy the inverter 172 for disabling the AND gate 180 which prevents the counter from being decremented by 26 2, which therefore keeps the counter from being decremented 27 below 0. Since the counter may never be allowed to have 28 a count greater than 5 from its three high order stages, 29 the gate 175 is enabled whenever a count of greater than 24 is detected b-y the decoder 126 such that a signal is ~; - - ~ .. .. .... .

1(~7~7t;~9~

1 provided on a line 107, and a count of 5 is detected by the decoder 164 such that a signal is present on the line 119 enabling the gate 175 to provide a signal output which is inverted by the inverter 178 for disabling the gate 174 such that the counter may not be incremented by 8.
It is seen that the counter 162 is incremented by 8 whenever there is a signal output from the gate 159, as illustrated in FIG. 5A, which is indicative of a state of high signal activity. The gate 180 is enabled for decrementing the counter by 2 whenever there is a state of intermediate signal act-ivity as manifested by a signal output from the OR gate 161 (FIG. 5A). The counter is decremented by 1 whenever the gate 170 is enabled, which occurs whenever the OR gate 163 (FIG. 5A) provides a signal output which is indicative of a state of low signal activity. It is to be appreciated that other gating arrangements and counting arrangements may be used in the practice of the present invention for selecting the modifier signal. The modifier signals which are manifested on the respective output lines from decoder 164, are in ascending order for increasing states of signal activity, that is the higher the state of signal activity, the higher is the multiplication factor which is applied to the gates 32 and 34 via line 36.

1(~776;~

1 Refer now to FIG. 6 and in particular FIG. 6A
2 which shows a portion of the delta value table 26. The 3 decoded signal appearing on the line 112 is applied at 4 any instant to a selected one of the gates 300, 302, 304, 306, 308, 310, 312 and 314, and the gates on FIG. 6B, with 6 one of these gates being enabled. Whenever the decoded 7 signal is 0 0 0 0, which is indicative of a state of high 8 signal activity, the gate 300 is enabled and a register ~ 301 provides a binary output which is indicati~e of the integer value ~48, which is the selected delta increment 11 and which is passed by the gate 300 to the output line 12 114 which is connected to the gates 32. The registers 13 301, 303, 305, 307, 309, 311, 313, 315 are all storage 14 registers or alternatively read-only memory devices which provide a binary signal output having a fixed integer value 16 which is gated out by its associated gate dependent upon 17 the binary coded signal appearing on the line 112. The 18 integer is in 2's complement form, with the most significant 19 bit being the sign bit. When the most significant bit is a 1, the integer is negative, and when the most 21 significant bit is 0 the integer is positive.
22 FIG. 6B is the remaining portion of the delta 23 value table which functions in a like manner to the portion 24 illustrated on FIG. 6A. Whenever the binary message 1 0 0 0 is present, the gate 316 is enabled for passing the 26 integer value -12, which is stored in the storage register 27 317, which selected delta increment is then passed to the 28 output line 114 which is connected to the gates 32. The 29 other gates and registers shown in FIG. 6B function in .

~77~;~4 1 a like manner in xesponse to the binary signal appearing 2 on the line 112.
3 Refer to FIG. 7 which illustrates in detail the 4 threshold table 30 illustrated in FIG. 5C. FIG. 7A
illustrates a portio~ of ~he threshold table, with the 6 gate~ 332-339 beln~ r~ponsive to the stora~e registers 7 340-347/ respective~y~ for ~assing the integer values 8 stored in the ~esp~tiVe re~i$t~rs in response to the 9 respective gates being enabled by the decoded signal appearing on the 1~ 112- FOE ~x~mple, when the decoded 11 signal appe~ring on the line 112 is 0 0 0 0, the gate 332 12 is enabled for passing the binary integer value -34 stored 13 in the register ~ t~ ~he output lln~ 112 for application 14 to the ga~g 34. Also, when the binary decoded message appearing on line 112 is 0 1 1 1, the gate 339 is enabled 16 for passing the ~ ry stored integer -1 ~tored in the 17 register 347 to the output line 118. Again, the integer 18 values are ~Jxp~gssed in 2's complement ~ithmetic.
19 F:[G. 7B illustrates the remaining portion of the threshold table 30 and includes gates 348~355 which when 21 enabled pass the binary integer value stored in the storage 22 registers 356-363, respectively. For example, when the 23 decoded binary message appearing on the line 112 is 24 1 0 0 0, the gate 348 is enabled for passing the binary integer value representing +1 which is stored in the register 356 26 which is then passed to the output line 118 for enabling 27 the gates 34. When the binary message appearing on the 28 line 112 is 1 1 1 1, the gate 355 is enabled for passing 29 the binary integer value representing the integer +34 as .

1~776Z4 1 stored in the register 363 which is then passed to the 2 output line 118.
3 Refer now to FIG. 8 whlch is a block diagram 4 representatiOn of the gate 120 which effects a multiplication of the selected delta increment by 1. The 6 8-bit word comprising the selected delta increment provided 7 on line 114 from the delta value table 26 is applied to 8 the gate 120. The first bit position is comprised of the 9 0 line 364 and the 1 line 365 which are connected to AND
gates 382 and 383, respectively, with the gate 382 providing 11 a signal output when the line 364 is active concurrent 12 with line 406 being active, which is indicative of a binary 13 0 for the first bit, and the gate 383 providing a signal 14 output when the line 365 is active concurrent with line 406 being active, which is indicative of a binary 1 for 16 the first bit. The eighth and most significant bit has 17 the 0 line 378 connected to an AND gate 396 and the 1 line 18 379 connected to an AND gate 397. The eighth bit is the 19 sign bit, th~t is when the 0 line 378 is active the delta increment is a positive number, and conversely when the 21 line 379 is active the delta increment is a negative number.
22 This is so since all arithmetic is performed in 2's 23 complement, such that all additions and subtractions may 24 be performed by the addition process. The intermediate bits are manifested on the lines 366-377, which enable 26 the gates 384-395, respectively. Gates 398-405 are high 27 order bits which assume the value of the sign bit. Whenever 28 the selected delta increment is a negative number as 29 manifested by the line 379 being active, a gate 140 is enabled for providing a source of logical 1 via a line ~ Y0973-005 -26-- : - . , ~. . . . ~
- . . ~ .

1~776Z~I

1 381 to the gates 399, 401, 403, and 405 to load l's in 2 the high order 4-bit positions. Conversely, when the delta 3 increment is a positive number as manifested by the line 4 378 being active, a gate 138 is enabled to provide the source of logical 0 via line 380 to gates 398, 400, 402 6 and 404, respectively, for loading O's in the four high 7 order bit positions. It is seen, therefore, that the most 8 significant bit position of the output of the gate 120, 9 that is, the 0 output from the gate 404 or the 1 output from the gate 405 is the sign bit which is indicative of 11 whether or not the modified selected delta increment is 12 a positive or negative number. In response to a signal 13 output from the gate 121 as manifested by the line 406 14 being active enabling the gates 382~405, the modified selected delta increment is provided on the output line 16 38 which is connected to the register 60 (FIG. 5C)~
17 Refer now to FIG. 9 which illustrates in detail 18 the gate 122 as illustrated in FIG. 5B. It is to be 19 remembered that the gate 122 effects a multiplication by 2 of the selected delta increment which appears on the 21 output line 144 from the delta value table 26. The first 22 through eighth bits of the selected delta increment are 23 provided on the lines 408-423, with the 0 line of the first 24 bit appearing on line 408 and the 1 line of the first bit appearing on line 409. The most significant bit, that 26 is the sign bit, has the 0 indication appearing on the 27 line 422 and the 1 indication appearing on the line 423, 28 with the line 422 being actiYe when the selected delta 29 increment is a positive number and the line 423 being active when the selected delta increment is a negative YO973-0o5 -27-., .

., . . - ,, , , - , .: - - ~ . - - .

~776Z4 1 number. The multiplication by 2 is effected by shifting 2 the eight bits by one place. This is effected by having 3 the lines 408 and 409 connected to the gates 427 and 428, 4 respectively, which are the second bit position of the output line. The first bit position of the output line 6 is from the output of a gate 426, which has a 0 forced 7 therein, by the following sequence. If the delta increment 8 is a negative number as manifested by the line 423 being 9 active, the gate 449 passes the source of logical 0 via a line 453 to an OR gate 425 for enabling the gate 426 11 to pass the logical 0 whenever the line 455 is active.
12 If the delta increment is a positive number as manifested 13 by the line 422 being active, the gate 450 passes the 14 source of logical 0 to the second input of the OR gate 425 for again enabling the gate 426. When the delta 16 increment is a positive number, the three high order stages 17 are forced to a zero condition as manifested by the gates 18 443, 445 and 447 being enabled by way of the line 454 in 19 response to gate 450 being enabled for passing the source of logical 0. Conversely, if the delta increment is a 21 negative number the gates 444, 446 and 448 are enabled 22 via the line 452 in response to the gate 451 being enabled 23 for passing the source of logical 1. It is seen, therefore, 24 that a 0 is forced into the low-order bit position as manifested at the output of the gate 426 and either a 0 26 or a 1 is forced into the three high-order bit positions 27 depending on the sign bit.
28 Refer now to FIG. 10 which illustrates in detail 29 the gate 124, which effects multiplication of the selected delta increment by 4D The multiplication by 4 is effected .

1C~776Z~

1 by shifting the eight bits by 2 places. The eight bits 2 from the delta value table 26 are manifested on the lines 3 460-476, with the 0 line and the 1 line of the first bit 4 being manifested on the lines 460 and 461, respectively, and which are applied to the third bit position of the 6 output line, namely the gates 481 and 482, respec`tively.
7 The most significant bit is manifested on the lines 475 8 and 476 which are connected to the gates 496 and 497, 9 respectively. Since the gate 124 effects multiplication by 4, the delta increment has to be shifted by three places, 11 and accordingly the first two bits of the output from gate 12 124 must have O's forced therein. Whenever the delta 13 increment is a positive number, as indicated by the line 14 475 being active, the gate 503 is enabled making the line 507 active which enables gates 477 and 478 to pass the 16 source of logical zero to enable the gates 479 and 480.
17 If the delta increment is a negative number as manifested 18 by the line 476 being active, the gates 504 and 502 are 19 enabled passing the source of logical 1 and 0, respectively The passed source of logical 0 enables the gates 477 and 21 478 enabling the gates 479 and 480, for again forcing O's 22 in the two low ordered bit positions. The line 505 is 23 activated for forcing l's into the two high order bit 24 positions, and the line 507 is activated for forcing O's into the two high order bit positions, and accordingly, 26 the shift by two, that is, the multiplication by 4, is 27 effected.
28 Refer now to FIG. 11, which is a detailed 29 illustration of the gate 126, which when enabled shifts the selected delta value increment by three places and .

62~

1 effects a multiplication by 8. This is accomplished by 2 connecting the 0 and 1 line 510 and 511, respectively, 3 of the first bit position of the selected delta increment 4 to the fourth bit position of the output line, that is, the gates 532 and 533, respectively. The eighth bit 6 position of the input delta increment as manifested on 7 the lines 524 and 525 are connected to the eleventh bit 8 position of the output line, that is, the gates 546 and 9 547, respectively. Zeros are forced into the three low order bit positions as follows. If the delta increment 11 is a negative integer, the line 525 is active, which enables 12 the gates 550 and 551 such that the source of logical 1 13 signal is applied via the line 555 to the most significant 14 bit position, that is, the gate 549 for loading a 1 into the most significant bit position, and a source of logical 16 0 is passed by the gate 551 making the line 554 active, 17 for causing the OR gates, 526, 527, and 528 to pass signals 18 to the gate 529, 530 and 531, respectively, for providing 19 a zero output indication from the three low order bit positions whenever the line 556 is active. If the selected ; 21 delta increment is a positive integer, the line 524 is 22 active enabling gate 552 to pass the source of logical 23 0 activating line 553 for enabling gates 526, 527, and 24 528 to pass signals to the gates 529, 530 and 531, respectively, for providing a zero output indication from 26 the three low order bit positions whenever the line 556 27 is active. Since line 553 is active, a zero is forced 28 into most significant bit position, gate 548. The lines 29 512-523 are the remaining delta increment input bits, and - ', ~ . ' -.

1~77624 1 the gates 534-547 are the remaining output bit positions 2 of the modified selected delta increments.
3 Refer now to FIG. 12 which illustrates in detail 4 the gate 128 which effects a multiplication of 16 of the selected delta increment. This is effected by shifting 6 the selected delta increment four places. The first bit 7 of the input delta increment as manifested on the lines 8 560 and 561 are applied to the fifth bit position of the g output modified delta increment word as manifested at the gates 585 and 586, respectively. Zeros are forced into 11 the first four bit positions by the following process.
12 If the input delta inarement is a negative number, the 13 line 575 is active, enabling the gate 603 to pass the 14 source of logical 1 signal via line 604 to the inputs of the OR gates, 576, 578, 579, and 580, respectively, which 16 in turn provide signal inputs to the AND gates 581, 582, 17 583, and 584, which provide zero output indications when 18 the line 607 becomes active in response to the gain logic 19 network re~uesting a modification or a multiplication factor of 16. Whenever the input delta increment is a 21 positive integer as manifested by the line 579 being active, 22 the gate 602 is enabled which passes the source of logical . .
23 0 to the gates 576, 578, 579, and 580, and in turn the 24 AND gates 581, 582, 583, and 584 provide zero bit indications at their outputs in response to the line 607 26 becoming active. The gates 587-600 are the remaining bit 27 position outputs for the modified selected delta increment, 28 with the gates 599 and 600 being the sign bit, with gate 29 599 being the sign bit for a positive integer, and the gate 600 being a sign bit for the negative integer.

:
.

~8771~

1 Refer now to FIG. 13 which is a detailed 2 illustration of the gate 130 which effects a multiplication 3 of 32 of the selected delta increment, that is, the selected 4 delta increment is shifted five places. The lower five order bit positions are forced to a logical 0 condition 6 in response to the line 627 becoming active, since the 7 source of logical 0 on line 626 is applied directly to 8 the five low order bit positions of gates ~28-632. The 9 first bit position of the input selected delta increment is manifested on lines 610 and 611 which are connected 11 to the sixth bit position of the output line, namely gates 12 633 and 634. The most significant bit, that is, the sign 13 bit, which is manifested on the lines 624 and 625 is 14 unconnected, since these sign bits in effect are overflow lS in the 2's complement arithmetic for the multiplication 16 by 32. The remaining bit positions of the input delta 17 increment as manifested on the lines 612-623 are applied 18 to the gates 635-646, inclusive.
19 ~efer now to FIG. 14 which is a detailed block 2Q diagram rep:eesentation of the decoder 70. The code symbol 21 sequence appearing on the line 20, manifests binary 1 22 indications when a line 721 is active, and manifests binary 23 0 indications when a line 722 is active. The lines 721 24 and 722 are connected to inputs of an OR gate 723 with the output of the gate being applied to the pulse generator 26 74, for synchronizing the pulse generator with the received 27 code symbol sequenc~. The 1 line 721 is connected to the 28 1 input of a flip-flop 70-0, and the 0 line 722 is connected 29 to the 0 input of the flip-flop 700. Flip-flops 700 through 705 form the respective stages of the storage register . .

1~776Z4 1 72. Gates 706-710 shift the binary information from the 2 flip-flops 700-705, respectively, to temporary storage 3 stages which comprise flip-flops 711-715, respectively, 4 at pul~e Q1 time. At pulse Q2 time, gates 716-720 shift the binary information from the flip-flops 711-715 to 6 storage register stages 701-705, respectively, a~ pulse 7 Q2 time. The binary states of the flip-flops 700-705 at 8 any instant of time respresent the present state of signal g activity of the received code symbol sequence. The decoder 76 is connected to all of the storage register stages for 11 determining the history of the received code symbol 12 sequence, with the output of the decoder 76 being applied 13 to the filter value table 82 illustrated in FIG. 14C.
14 ~he decoder 80 is connected to the last four stages, that is, flip-flops 702-705 of the storage register 72 for 16 providing a history of the received code symbol sequence 17 to the delta value table 84 illustrated in FIG. 14B. The 18 decoder 78 is connected to the stages 701-704 of the storage 19 register 72 for providing a history of the received code

5~mbol se~ue;nce to the gain logic network 86.
21 The delta value table 84 and the gates 88 22 illustrated in FIG. 14B are similar to the delta value 23 table 26 and gates 32 for the encoder portion of the delta 24 modulator ~et forth in FIG. 5B, so a detailed description of the fu~ctioning of these elements isn't repeated. The 2~ gates 87 ~ssociated with filter value table 82 illustrated 27 in FIG. l~C are similar to the gates 34 illustrated in 28 FIG. 5C, and accordingly a detailed description of the 29 functioning of these gates isn't repeated. The gain logic network 86 illustrated in ~IG. 14D is similar to the gain ~ . :
.

1077~;Z4 1 loyic network 28 illustrated in FIG. SD and accordingly 2 a detailed description of its functioning isn't repeated.
able 82 is illustrated i d operation is described h ~he gain logic network 86 (FIG. 14D) responds

6 to the state of signal activity as represented by the

7 decoded signal at the output of the decoder 78 (~IG. 14A) f

8 for selecting a new modification signal at pulse time Q3

9 when the 8-bit counter 162~ is either incremented or decremented or left in its present condition as previously ,¦
11 eleCted modification sig 1 ~¦
12 of the decoder 164' is provided on an output line 724 and ,¦
13 is applied to the gates 87 and 88, respectively, for ¦
14 providing the multiplication factor for modifying the ¦
selected smoothing value and the selected delta increment, l¦
16 respectively.
17 ~ complete timing se~uence for the decoder 70 , 18 is now described for one cycle of system decoding operation.
19 At pulse time Ql the received code symbol sequence presently stored in the il-put storage register 72 is shifted from 21 the shift register stages 701-705 to temporary storage c' 22 stages 711-715, as previously described. At pulse Q2 time, ¦
23 ormation stored in the te 24 stages 711-715 are shifted to the storage register stages 701-705 as previously described. At Q2 time the old sum 26 stored in the accumulator 99 is shifted in parallel through 27 the gate 100 to the data register 101 for addition with 28 the modified selected reference value presently stored ~¦
~9 in the register 91. At pulse Q3 time the gain l~gic network ¦
86 responds to the decoded message from the decoder 78 Y0973-oos _34_ .
., ~ , ,- ~ - .

1 (FIG. 14A) for generating a new modification signal on 2 output line 724 which is applied to the gates 87 and 88, 3 respectively. At pulse Q4 time, the modification signal 4 on line 724 enables a selected one of the gates 121'', 123'', 125'', 127'', 129'' and 131'', and whichever of 6 these gates is enabled by the modification signal modifies 7 the selected delta increment signal from the delta value 8 table 84, and this modified delta increment is applied 9 via the line 90 to the register 91, and is added with the information presently stored in the register 101. At pulse -11 Q5 time, the old sum from the adder 92 is passed through 12 the gate 94 and stored in the register 101 for forming 13 a new sum output from the adder 92, and this new sum is 14 passed by the gate 95 to the accumulator 99. At pulse Q6 time, a selected one of the gates 121'" , 123''', 125''', .. . . .. ..
16 127' ", 129''', and 131''' is enabled for enabling a 17 selected one of the gates comprising gates 87 for modifying 18 the selected smoothing value from the filter value table 19 82, with the modified smoothing value being applied via the line 90 to the register 91 for addition with the 21 information presently stored in the register 101. At pulse 22 time Q7 the sum from the adder 92 is passed by the gate 23 93 to the register 96 to a digital analog converter 97 : 24 with the reconstructured analog signal, which is a representation of the input signal set forth in FIG. 1 26 and FIG. 5 being applied to the analog receiver 98. This 27 timing cequence repeats for the duration of system 28 operation.
29 Refer to FI~. 15, which is a detailed showing of the filter value table 82 as illustrated in FIG. 14C.

~- Y.)973-005 -35-Z~

1 The filter ~alue -table responds to the decoded message 2 output from the decoder 76 for providing a smoothing value 3 for the decoded delta increment, with the smoothing value 4 being selected in accordance with the state of signal activity of the received code symbol sequence. The 6 smoothing values are one of a plurality of positive or 7 negative integers in 2's complement configuration which 8 are selected by a gating process to be described below 9 With reference to FIG. 15A, when the decoded signal has a signal state represented by the binary configuration 11 0 0 0 0 0 0, a gate 731 is enabled for passing the integer 12 value -92, which is stored in a storage register 730.
13 This signal is applied to the gates 87 for modification 14 as previously described. ~ gate 733 passes the integer value -8 stored in the register 732 whenever the decoded 16 message has a binary configuration of 0 0 0 1 1 1. The 17 binary configurations and associated gates and registers 18 situated between the registers 730 and 732 operate in a 19 similar manner.
FIG. 15B illustrates another portion of the 21 reference value table, with a gate 735 being enabled when 22 the binary configuration 0 0 1 0 0 0 is present, which 23 allows the integer value -6 which is stored in the register 24 734 to be applied to the gates 87 for modification. A
gate 737 passes the integer value -2 stored in a register 26 736 when the decoded binary configuration is 0 0 1 1 1 1. -27 The registers and gates situated intermediate the registers 28 734 and 736 operate in a similar manner.

.~ :

- . - . . .
- - . .

1~77624 1 In FIG. 15C another portion of the filter value 2 table is illus-trated with the gate 739 being enabled when 3 a binary configuration of 0 1 0 0 0 0 is sensed, which 4 permits an integer value of +2 to be passed from the storage S register 738 to the gate 86. A gate 741 is enabled when 6 the binary configuration 0 1 0 1 1 1 is sensed, ~ermitting ,7 the integer value of +6 stored in a register 740 to be 8 applied to the gates 87. The gates and associated registers 9 situated intermediate the registers 738 and 740 operate in a similar manner.
11 FIG. 15D illustrates another portion of the filter 12 value table 82, with the gate 743 being enabled in response 13 to the decoded message having a binary configuration of 14 0 1 1 0 0 0, for passing the reference integer value +7 from the storage register 742 to the gates 87. A gate 16 745 is enabled in response to the decoded binary 17 configuration of 0 1 1 1 1 1, for passing the positive 18 integer value +18.from the storage register 744 to the 19 gates 87. The gates and storage register stages intermediate the storage registers 742 and 744 operate 21 in a similar manner.
22 FIG. 15E illustrates another portion of the filter 23 value table 82 with the gate 747 being enabled in response 24 to the binary configuration 1 0 0 0 0 0 for passing the integer value -18 from the storage register 746 to,the 26 gates 87. A gate 749 is enabled in response to the binary 27 configuration 1 0 0 1 1 1 for passing the integer value 28 -7 from the storage register'748 to the gates 87. The 29 gates and storage register stages intermediate the storage registers 746 and 748 operate in a similar manner.

YO973-OOS ' -37-,.

.

~776Z4 1 FIG. 15F illustrates yet another portion of the 2 filter value table 82. A gate 751 is enabled in response 3 to the provision o~ the binary configuration 1 0 1 0 0 0 4 for passi~g the inteyer value -6 from the storage register 750 to the gates B7. A gate 753 is enabled in response 6 to the provi6ion of the binary configuration 1 0 1 1 1 1 7 for passing the integer value -2 from the register 752 8 to the gates 87. The gates and register stages intermediate 9 the registers 750 and 752 operate in a similar manner.
FIG. 15G illustrates another portion of the filter 11 value table 82, with the gate 755 being enabled in response 12 to the binary configuration 1 1 0 0 0 0 for passing the 13 integer value +2 from the storage register 754 to the gates 14 87. A gate 757 is enabled in response to the binary configuration 1 1 0 1 1 1 for passing the integer value 16 +6 from the storage register 756 to the gate 87. The gates 17 and registers intermediate the register stages 754 and 18 756 operate in a similar manner.
19 Another portion of the filter value table 82 is illustrated in FIG. 15~ with a gate 759 being enabled in 21 response to the binary configuration 1 1 1 0 0 0 for passing 22 the integer value ~8 from the storage register 758 to the 23 gates 87. A gate 761 is enabled in response to the 24 provision of the binary configuration 1 1 1 1 1 1 for passing the integer value +92 from the storage register 26 760 to the gates 87. The gates and storage register stages 27 intermediate the registers 758 and 760 operate in a similar 28 manner.

.

: .
-: . . -: - ,, - - . - . :

1~377624 1 In summary, a delta modulator has been disclosed which generates code symbols representing increments of signal level, with each code symbol being determined in accordance with the difference in signal level between an input signal and a prediction signal, which is a representation of the input signal, with the prediction signal being formed by accumulation of successive signal level increments which depend on the history of the code symbols. There is means for storing a sequence of generated code symbols, with the sequence including the most recent code symbol and a given number of preceding code symbols, with the pattern of code symbols at any instant definingthe state of signal activity. There is also means for producing three signals in accordance with the state of signal activity represented by the stored code symbol pattern, namely an incremental signal level, a threshold value and a modifier signal. Further, there is means for modifying the incremental signal level and the threshold value an amount determined by the modifier signal.
Finally, there is means for forming a new prediction signal by accumulation of successive modified signal level increments which are summed with successive modified threshold values, including means for generating a new code symbol in response to comparing the new prediction signal with the input signal.

. ' .

_ 39 , . .
- . . ~ . .

Claims (10)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a delta modulator, a method of generating code symbols representing increments of signal level, with each code symbol being deter-mined in accordance with the difference in signal level between an input signal and a prediction signal which is a representation of said input signal, with said prediction signal being formed by accumulation of successive signal increments which depend on the history of said code symbols, said method comprising the steps of:
storing a sequence of generated code symbols, said sequence including the most recent code symbol and a given number of preceding code symbols, with the pattern of stored code symbols at any instant defining a state of signal activity;
selecting three signals in accordance with the state of signal activity represented by the stored code symbol pattern, namely an incremental signal level, a threshold value and a modifier signal;
modifying said incremental signal level and said threshold value an amount determined by said modifier signal;
forming a new prediction signal by accumulation of successive modified signal level increments which are summed with successive modified threshold values; and generating a new code symbol in response to comparing said new prediction signal with said input signal.

2. In a delta modulator, a method of generating code symbols as defined in claim 1 wherein said modifier signal is a multiplier signal, said selecting step includes selecting a multiplier signal, having an integer value, in accordance with the state of signal activity represented by the stored code signal pattern, and said modifying step includes multiplying said incremental signal level and said threshold value by the selected multiplier signal.

3. In the method of claim 1 further comprising a method of decoding the code symbols, said method of decoding comprising the steps of:
storing a sequence of said code symbols, said se-quence including the most recent code symbol and a given number of preceding code symbols, with the pattern of code symbols at any instant defining a state of signal activity;
selecting an incremental signal level in accordance with the state of signal activity represented by the stored code signal pattern;
selecting a smoothing value in accordance with the state of signal activity represented by the stored code signal pattern;
selecting a multiplier signal, having an integer value, in accordance with the state of signal activity represented by the stored code signal pattern;
multiplying said incremental signal level and said smoothing value by the selected multiplier signal; and forming a decoded signal in response to accumulat-ing successive multiplied signal level increments which are summed with successive multiplied smoothing values.

4. In a delta modulator, a method of generating code symbols as defined in claim 1 wherein said code symbols are binary code signals and said prediction signal is an analog prediction signal wherein a given binary code signal has one binary state when an analog input signal has a signal level greater than or equal to the signal level of said analog prediction signal, and said given binary code signal has the other binary state when said analog input signal has a signal level which is less than the signal level of said analog prediction signal, said selecting step comprising:
selecting a binary coded incremental signal level in accordance with the state of signal activity represented by the stored binary code signal pattern;
selecting a binary coded threshold value in accordance with the state of signal activity represented by the stored binary code signal pattern;
and selecting a binary coded modifier signal in accordance with the state of signal activity represented by the stored binary code signal pattern, said modifying step comprising:
modifying the respective binary bit patterns of said binary coded incremental signal level and said binary coded threshold value in accordance with the binary bit pattern of said binary coded modifier signal;
said forming step comprising:
forming a binary coded prediction signal by accumulation of successive modified binary coded incremental signal levels which are summed with successive modified binary coded threshold values; and converting said binary coded prediction signal to an analog prediction signal; and said generating step comprising:
generating a new binary code signal in response to comparing said analog input signal with said analog prediction signal.

5. In the method of claim 4 further including a method of decoding the binary code symbols generated, said method of decoding comprising the steps of:
storing a sequence of the generated binary code symbols, said sequence including the most recent binary code symbol and a given number of preceding binary code symbols, with the pattern of stored binary code symbols at any given instant defining a state of signal activity;
selecting a binary coded incremental signal level in accordance with the state of signal activity represented by the stored sequence of the generated binary code symbols;
selecting a binary coded smoothing value in accord-ance with the state of signal activity represented by the stored sequence of the generated binary code symbols;
selecting a binary coded modifier signal in accord-ance with the state of signal activity represented by the stored sequence of the generated binary code symbols;
modifying the respective binary bit patterns of said binary coded incremental signal level and said binary coded smoothing value in accordance with the binary bit pattern of said binary coded modifier signal;
and forming a decoded binary signal in response to accumulating successive modified binary coded incremental signal levels which are summed with successive modified binary coded smoothing values.

6. The method of claim 5, including the step of:
converting said decoded binary singal to an analog signal.

7. In a delta modulator for generating code symbols representing increments of signal level, with each code symbol being determined in accordance with the difference in signal level between an input signal and a prediction signal which is a representation of said input signal, with said prediction signal being formed by accumulation of successive signal level increments which depend on the history of said code symbols, the combination comprising:
means for storing a sequence of generated code symbols, said sequence including the most recent code symbol and a given number of preceding code symbols, with the pattern of code symbols at any instant defining a state of signal activity;
means for producing three signals in accordance with the state of signal activity represented by the stored code symbol pattern, namely an incremental signal level, a threshold value and a modifier signal;
means for modifying said incremental signal level and said threshold value an amount determined by said modifier signal; and means for forming a new prediction signal by accumulation of successive modified signal level increments which are summed with successive modified threshold values, including means for generating a new code symbol in response to comparing said new prediction signal with said input signal.

8. In a delta modulator as defined in claim 7 wherein said modifier signal is a multiplier signal and said means for producing three signals comprises means for selecting an incremental signal level in accordance with the state of signal activity represented by the stored code signal pattern;means for selecting a threshold value in accordance with the state of signal activity represented by the stored code signal pattern, and means for selecting a multiplier signal in accordance with the state of signal activity represented by the stored code signal pattern.

9. The combination claimed in Claim 8, including delta demodulation means comprising:
means for storing a sequence of said generated code symbols, said sequence including the most recent code symbol and a given number of preceding code symbols, with the pattern of code symbols at any instant defining a state of signal activity;
means for selecting an incremental signal level in accordance with the state of signal activity represented by the stored code signal pattern;
means for selecting a smoothing value in accordance with the state of signal activity represented by the stored code signal pattern;
means for selecting a multiplier signal in accordance with the state of signal activity represented by the stored code signal pattern;
means for multiplying said incremental signal level and said smoothing value by the selected multiplier signal; and means for generating a decoded signal which is a representation of said input signal in response to accumulating successive multiplied signal level increments which are summed with successive multiplied smoothing values.

10. In a delta modulator as defined in claim 7 wherein said modifier signal is a multiplier signal, said means for producing three signals includes:
decoder means for decoding the stored sequence of generated code symbols for providing a decoded signal in-dicative of the state of signal activity at a given in-stant;
means for selecting one of a plurality of stored in-cremental signal levels in response to the provision of said decoded signal;
means for selecting one of a plurality of stored threshold values in response to the provision of said de-coded signal; and means for selecting one of a plurality of multiplier signals, each having a different integer value, in response to the provision of said decoded signal; and said means for modifying includes:
means for multiplying the selected one of said stored incremental signal levels by the selected one of said multiplier signals; and means for multiplying the selected one of said stored threshold values by the selected one of said multiplier signals.