SU1550509A1 - Scaling device - Google Patents

Abstract

The invention relates to automation and computing, mainly to digital signal processing, and can be used to convert various data arrays to a predetermined format. The aim of the invention is to expand the scope of application by reducing the data set to the specified format. The scaling device comprises AND elements 26, shapers 4 and 5 pulses of write and read, respectively, counters 7 and 10, blocks 8 and 12 of the memory of the write and read address, register 9, comparison circuit 11, multiplexer 13 and information memory block 16 with appropriate communications. 3 il.

Description

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The invention relates to automation and computing, mainly to digital signal processing, and can be used to convert various data arrays to a predetermined format.

The purpose of the invention is to expand the scope by reducing the data set to the specified format,

I Figure 1 shows a scaling device;; Fig. 2 is a timing diagram of the operation of the device for scaling in the reception mode, information; FIG. 3 is a time diagram of the operation of the device for scaling in the information output mode;

The device contains a clock input 1 of the device, the first element AND 2, the output 3 of the device reception permission, the driver 4 of the write pulse, the generator 5 of the read pulse, the second element And 6, the first counter 7, the block 8 of the write address memory, register 9, the second counter 10, compare circuit 11, read address memory block 12, multiplexer 13, device information 14, device information output 15, device memory 16, output 17 of device termination, signal output 18 of the device and resolution 19 svydachi device.

The timing diagram in figure 2 for C- ,, is the address of the record through the multiplexer 13

45

Even device operation when receiving Information from (4x2k +4) array fragments:

sync pulses 1 gates the arrival of 4 data fragments; before

signal 2 is input 3, i.e. corresponds to the device mode, which determines the selective recording of array fragments;

signal 3 is the access signal to (5 block of memory 16 from the output of driver 4 by the write enable signal from the first output of block 8 of memory;

signal 4 corresponds to the formation of the recording addresses and their values at the second output of the memory block 8 and the output of the multiplexer 13.

The time diagram in FIG. 3 shows the operation of the device when forming a linearly scaled data array consisting of (2k + 1) fragments, obtained by selective reading from the recorded (3 x 2 +1) fragments. In FIG. 3 it is indicated:

50

55

arrives at memory block 16. A recording pulse forming circuit 4, which implements a function of logical multiplying input signals and generating a recording signal by level and duration, generates a signal for recording a piece of data into memory block 16. Upon completion of the data array entry, the last g scaled write address is stored in register 9 at input 19 and a signal is generated that puts the device into scaling mode when reading the recorded data. The second element And 6 stops transmitting clock pulses, and the first element And 2 starts transmitting clock pulses from input 1, which accumulate on the first counter 7, Block 12 of memory, implemented by means of the ROM according to the current value of the contents of the counter 7 and according to the value of the final address of the record stored the register in register 9, generates a read enable signal and a read address so that

0

1 corresponds to the formation of a read mode signal at the input 19 of the device; 2 - sync pulses from input 1; 3 - signal for accessing the memory block 16 from the output of the driver 5 according to the read enable signal from the first output of the memory block 12; 4 corresponds to the formation of reading addresses and their values at the second output of memory block 12 and the output of multiplexer 13.

The device works as follows.

Input 14 receives a fragment of the data array, and a single level is established at input 3.

Element 6 transmits clock pulses that are accumulated on counter 10, memory block 8 implemented by means of ROM, generates addresses and write enable signal so that from groups of parameter values or fragments of an array with numbers from 1 to 2

five

f +1 records

each parameter; from 2

- every second parameter;

up to 2

from 2

K + -2

+ 1 to 2

0

parameter and t0d

- every fourth from 2K + +1 to 2K

every 2 parameter; where 2 minimum parameter format.

As the input data redundancy increases, the scale factor increases as it is recorded. New

five

0

five

enters the memory block 16. The feed pulse 4 forcing device 4, which implements the function of logical multiplying the input signals and generating the recording signal according to the level and duration, generates a signal for inserting a piece of data into the memory block 16. Upon completion of the data array entry, the last g scaled write address is stored in register 9 at input 19 and a signal is generated that puts the device into scaling mode when reading the recorded data. The second element And 6 stops transmitting clock pulses, and the first element And 2 starts transmitting clock pulses from input 1, which accumulate on the first counter 7, Block 12 of the memory, implemented by means of the ROM on the current value of the contents of the counter 7 and according to the value of the final address of the record that stores in register 9, generates a read enable signal and a read address so that

five

from the groups of parameters or fragments of the arrays, recorded at the first stage of scaling with numbers from 1 to 2-2k, every 2nd parameter was read; from 2-2 +1 to 3-2 l each

 parameter; from r.2k +1 to the final — every 2 ° parameter, where c is a positive part of the ratio of the final address when reading to -2k.

The read address through multiplexer 13 goes to memory block 16, from which reads from the output of shaper 5, implementing the function of logical multiplication of input signals and generating a read signal by level and duration, are read into the device 15 output. When the value of the final address of the record stored in register 9 coincides with the current value of the contents of the first counter 7, the comparison circuit 12 generates a signal at the output 17 of the device.

The device allows adaptively without the operator to scale the facsimile data arrays that have a wide range of parameters in the absence of data on the size of the original array, which also reduces the memory required to store redundant information as it enters the scaling device. °

Claims (1)

Invention Formula A scaling device comprising a first AND element, a write pulse shaper, a first counter and an information memory block, the information input of the device connected to the information input of the information memory block, a clock input and a output resolution input of the device connected respectively to the first and second inputs of the first element And, characterized by the fact that 0 five 0 five 0 in order to expand the scope of application by converting the data array to the specified format, it contains a read pulse shaper, a second AND element, a write address memory block, a register, a second counter, a comparison circuit, a read address memory block and a multiplexer, with the output of the first element And it is connected to the counting input of the first counter and to the information input of the read pulse driver, the POWER of which is connected to the read input of the information memory block and is the signal output of the device; the enable input is and which is connected to the first input of the second element I, the register recording resolution input and the control input of the multiplexer, the output of which is connected to the address input of the information storage unit whose output is the information output of the device, the clock input of which is connected to the second input of the second element AND, the output of which is connected to the counting input of the second counter and the information input of the recording pulse shaper, the output of which is connected to the recording enable input of the information memory block, the output of the second counter c one with an address input unit memory write addresses, the first and second outputs koto connected to the resolution input of the write pulse generator, with the combined information input of the register and the first information input of the multiplexer, the register output is connected to the first input of the comparison circuit and to the first address input of the memory of the reading address, the first and second outputs of which are connected respectively to the enable input of the read pulse shaper and the second information input of the multiplexer, the output of the first counter is connected to the second address input of the memory of the address reading and the second input of the comparison circuit, the output of which is the output of the device operation end, four I J. N " Compiled by A. Klyuev Editor L.Pcholinska Tehred M.Didyk Order 273 Tirah 558 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 I Proofreader Н0Ревска Subscription