SU1543406A2 - Device for single-side shifts of binary codes with check - Google Patents

Abstract

The invention relates to computing and can be used in high-speed digital computer processors. The purpose of the invention is to increase the reliability of the control. The device contains nodes 1, 2 shift information, node 3 shift check bits, node 4 shift group of bits, the first and second nodes 5, 6 modulo two convolution, first node 7 comparison, first switch 8, first information input 9 of the device, group 10 modulo two nodes, device information output 11, device control output group 12, device 3 third convolution node 13, second comparison node 14, element OR 15, device failure output 16, device group offset value input 17, input 18 set the value shifting the device bits, the second information input 19 of the device, the inputs 20, 21 of the control bits of the device, the second switch 22, the third comparison node 23, the fourth convolution node 22 modulo two. The device provides continuous control modulo two. The goal is achieved by introducing a modulo-two fourth convolution node, a third comparison node and a second switch, providing control of the extreme opposite of the shift direction of the group of bits being moved in. 1 il.

Description

The invention relates to computing, can be used in processors of high-speed computing systems and is additional to> $ auth, sv. No. 1446617.

The aim of the invention is to increase the reliability of control.

The drawing shows a functional diagram of the device. 10

The device contains information shift nodes 1 and 2, control bit shift node 3, bit group shift node 4, first 5 and second 6 convolution nodes in the middle two, the first comparison node 7 15, the first switch 8, the first information input 9 of the device, group 10 convolution nodes modulo two, information output 1J of the device, a group of 12 outputs of the control 20 bits of the device, the third node 13 convolution modulo two, the second node> 14 comparison, element OR 15, output 16 of the device malfunction, input 17 sets the magnitude of the shift groups of devices 25st, entrance 18 quests in the values of the shift bits of the device, the second information input 19 of the device, inputs 20 and 21 of the control bits of the device, the second switch 22, the third node 23 of the comparison, the fourth node 24 convolution modulo two.

The first node 1 shift information provides a shift of the binary N-bit code received at the first 35 information input 9 of the device in one direction (for example, to the right) by the Number of bits that is a multiple of K, where K 5: 2, and through the second information input 19 of the device the corresponding number of groups of bits of K bits in each group is carried out before moving into the released bits (left).

The number of groups of bits of K bits 45 in each group is set by setting the corresponding code at the device input 17, the value (M) of which can be 0, 1, 2, ..., where [xj means the nearest integer, smaller X.

Moreover, in node 1, the codes are shifted to the right (with the described: pushing) by the number, respectively, _ςΐξ

0, 4, 2K

In node 2, a shift (to the right) of the code set to

the course of node 1, with the bits of the code installed at the output of the switch 8 inserted into the released bits (left) by the number of bits equal to w, where m = 0, 1, 2, ..., (K-1). In this case, the shifted and shifted codes are transmitted to the information output 11 of the device. The code of the amount of shift within 0 £ ha Sr (K-l) is set at the input 18 of the device.

The resolution of the output 11 of the device is N, and the outputs of the retractable number of nodes 2 and 4 are (K-1), i.e. the last bit of the output of the switch 8, with respect to the direction of the shift, is used, the number of bits of which is K.

Node 3 functions in the same way as node 2, with the difference that the width of its input 20 and output is ( ⁺ O. The bit depth of the input of the retractable number of the node is LV ^{(without the} last from the direction of the shift direction of the discharge of input 2J, the width of which is + J).

Node 4 functions in the same way as node 2, with the difference that the capacity of its inputs and the retractable numbers is K and K-1, respectively.

The switch 8 is designed to transmit the output of the first bit signals relative to the direction of the shift of the not moved group of code bits from input 19.

The switch 22 is designed to transmit to the output of the parity signal (from input 21) a group of bits (code installed at input 19), the signals of which are transmitted to the output of switch 8.

For example, if you number the groups of bit codes on the inputs 19 and 9 of the device (and, therefore, the groups of bits of the inputs 19 and 9) in accordance with the direction of the shift (for example, to the right) with the numbers 0, 1, 2, ..., then when setting to input 18 of the code with a value equal to 3 of the group. bits of code at input 19 with numbers 0, 1, 2 will be shifted into the shifted code at the output of node 1 of the shift, and the signals of the group of bits with number 3 using switch 8 will be transmitted to it exit.

The device operates as follows.

In the initial state, an N-bit shift code is set at the input 9 of the device, a shift code is set at the input 19 of the device. At the input 20 of the device is tired, G N Ί,. a ((jg- '+ 1) -bit code of control signals is generated, the value of which in each ith digit corresponds to the sum modulo two signals in the corresponding ith group. bits of the code at input 9, where i = 0, 1,. .., N-1 At the input 21 of the device, a code of control signals is set, the value of which in each category, as for input 20 of the device ·, corresponds to the sum modulo two signals in 20 of the corresponding group of bits of the code at the input 19 of the device. code of shift values by the number of digits, a multiple of K, i.e. groups GUSTs

N N Ί bits And, where 0 <M <-g-j. At the input 18 of the device sets the code value of the bit shifts in the range 0 <K-1.

The code installed at input 9 of the device, for example, different 1111011100110001 (with N = 16), is shifted in node J, for example, to the right by M, K = 2; 4 = 8 bit 'for M = 2, K = 4y, ac input device 19 is pushed into the vacated bits The corresponding part of the code equal to, for example, 111011100410001. The result at the output node 1 information sfor- ₄ shift θ miruetsya code 0011000111110111. The code of control bits set at the input 20 of the device and equal to 0101 is shifted to the right in node 3 by И = 2 'bits, and the code installed at the input ₄ d ^J 21 of the device and equal to 101 is inserted in the node 3 into the released bits on the left' by two digits on the right side of the code. As a result, the code 0101 will be generated at the output of the shift node 3. With qq, the logical unit will be set to the rightmost bit of the output of the shift node 3, and the code 010 will be set at the outputs of the remaining bits. Of the groups of bits 0001, OOP, 0111, 111 of the input 19, gg When counting from the direction of shift (i.e., against the direction of shift), signals 0111 of signal group 0100 are transmitted to the output of switch 8, and signals 111 of signal group 0111, transmitted to output 24, are transmitted to the inputs of the retractable numbers of nodes 2 and 3.

In node 2, a shift to the right of the code installed at its input, a shifted number, and equal to 0С11000111110111, by the number of bits equal to, for example, three (that = 3), is carried out. At the same time, the three right bits of the code are shifted to the released bits in node 2.

As a result, the code 1110011000111110 is set at the output of the 11 device. The code 0111 will be set at the input of the shifted number of the node 4. The code will be generated at the output of the shift node 4 (as a result of shifting the code to the right, equal to 0111, by w = 3 bits and moving it from the output of the switch 8 of code 111), equal to 1110. In node 6, a sum signal is generated modulo two code signals of the bits from the outputs of nodes 4 and 3, respectively 1110 and 010. A logical zero is generated at the output of node 6. At the output of node 5, a sum signal is generated modulo two signals of the bits of the code generated at the output of the device 11, which in this case is equal to logical zero. The first node 7 compares the outputs of nodes 5 and 6 of the convolution modulo two with the formation of a logical zero at the output, which means that errors in nodes 1 and 2 did not occur (i.e., nodes 1 and 2 are operational ^. In case of inequality of signals on its Inputs node 7 forms a logical unit, which means that a malfunction (or interference) has occurred in the device.

The signal from the output of the comparison unit 7 is transmitted via the OR element 5 to the output 16 of the device malfunction.

The error signal at the output of the first comparison node 7, however, does not provide complete control of the health of the device (i.e., high reliability of the functional control), since error control ¹ is not ensured in groups of code bits installed at input 19, transmitted at the output of switch 8 and input and output circuits of discharges of the extreme direction of the shift (extreme right) of the group of discharges of node 1. Control of these circuits is provided using nodes and elements 15, 13, 14, 23, 24 and switch 22.

At node 13, a sum signal is generated modulo two dye discharge signals in the direction of the shift of the information output group of the first information shift node 1. In this case, the summation result is 1 ”. The second comparison node 14 compares the result of the convolution with the extreme discharge in the direction of shift of the high of the node 3 of the shift of the control bits. If incomparable, a single signal from the output of the second comparison node 14 through the OR element 15 passes to the output 16 of the device malfunction. At node 24, a sum signal is generated modulo two bit signals from the output of switch 8. In this case, the summation result is “1”. The third comparison node 23 compares the result of the convolution with the output of the switch 22. In case of non-comparison, a single signal from the output of the third comparison node 23 passes through the OR element 15 to the output 16 of the device malfunction. The convolution nodes modulo two groups of 10 form the control bits of the K-bit groups of the number generated on the second node 2 of the information shift, which are received by the outputs of the control bits of the device of group 12.

Claims (1)

SUMMARY OF THE INVENTION A device for one-sided shifts of binary codes with control by jq ed. St. No. 1446617, characterized in that, in order to increase the reliability of control, a second switch, a third comparison node and a fourth verification node, 5 current modules modulo two are introduced into it, and the input of setting the shift value of the device is connected to the control input of the second switch, the information input of which connected to the second input of the control bits of the device, the output of the second switch is connected to the first input of the third comparison node, the second input of which is connected to the output of the fourth convolution node modulo 25 two, the input of which is connected to by the first switch, the output of the third convolution node modulo two is connected to the third input of the OR element.