SU1538278A1 - Line frequency signal enerator - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to expand the functionality by additionally generating a frame frequency signal and ensuring separate adjustment of the amplitude of the horizontal frequency signal and the frame frequency signal. The r-s signal of the horizontal frequency contains r-r 1 clock pulses, counters 2 and 5, D / A converter 3, memory block 4, inverter 6 and switch 7. Counter 2 counts the pulses from r-1, and the received multi-digit code goes to DAC 3. At its output, a voltage linearly during the line is formed, i.e. horizontal frequency signal. Using the counters 2 and 5, the D / A converter 3, and the memory block 4, a frame frequency signal is generated. For separate adjustment of the amplitude of the horizontal and frame frequency signals, a switch 7 is inserted, which connects to the reference input of the DAC 3 during the synchronizing pulses of the lines the voltage setting of the amplitude of the frame frequency signal, and the rest of the time - voltage setting of the amplitude of the horizontal frequency. 1 hp f-ly, 1 ill.

Description

ate

00

oo 1C 1

OO

31

The invention relates to digital oscillators and can be used to obtain periodic sawtooth voltages with a row frequency and a field, for example, to generate sweep signals in rows and across fields.

The purpose of the invention is to expand the functionality by additionally generating a frame frequency signal and separately adjusting the amplitude of the horizontal frequency signal and the frame frequency signal.

The drawing shows an electrical block diagram of a horizontal frequency signal generator).

The horizontal frequency signal generator contains serially connected clock generator 1, the first counter 2, the digital-to-analog converter 3 and the memory block 4, the second counter 5, the inverter 6 and the switch 7. The output of the digital-analog converter 3 is the horizontal frequency signal output, the output of the memory block 4 This is the frame frequency output. The gate input of the second counter 2 is the input of the clock pulses of the rows and is connected to the counting input of the second counter 5 with the control input of the memory block 4, with the control input of the switch 7 and through the inverter 6 with the reset input of the first counter 2, the reset input of the second counter 5 is a frame clock input. The outputs of the second counter 5 are connected respectively to the installation input

0

five

0

five

0

five

The second counter 5 counts the pulses arriving at the input of the synchronizing pulses of the rows. At the moment of arrival of the synchronizing pulse of the rows to the gate input of the first counter 2, the contents of the second counter 5 are overwritten into the first counter 2. At the output of the digital-to-analog converter, a signal is generated whose amplitude corresponds to the number of synchronized pulses of the second counter counted by the second counter. This signal is memorized in memory block 4, since at this moment a synchronizing pulse of strings arrives at its control input. At the output of memory block 4, the memorized signal is maintained for the entire row until the next clock pulse of the rows arrives. A frame frequency signal is generated.

At the end of the synchronizing pulse of the rows, the inverter 6 generates a reset pulse that zooms in on the first counter. The zeroing of the second counter 5 is performed by the frame clock pulses applied to its reset input.

The amplitude of the signal at the output of the digital-to-analog converter 3 is adjusted by changing the voltage at its input to the reference voltage. At the same time, for separate adjustment of the amplitude of the line frequency signal and the frame frequency signal, the voltage to the input voltage of the reference digital-to-analog converter is supplied from the output of switch 7, which

45

The first counter 2 is connected. The output of the commutator 4Q is connected to the input of the reference torus 7 and is connected to the input of the reference voltage of the digital-to-analog converter. The first input of the switch 7 is an input voltage of setting the amplitude of the horizontal frequency signal. The second input of the switch 7 is the input voltage for setting the amplitude of the frame frequency signal.

The signal generator line frequency works as follows. Q

The first counter 2 counts the pulses arriving at its input from the clock pulse generator 1. The multi-digit code from the output of the first counter 2 is fed to the input of the digital-to-analog converter 3, at the input of which a voltage is generated linearly during the row - a horizontal frequency signal.

ch55

the voltage of the digital-to-analog converter during the synchronizing pulses of the lines; the voltage is set to the amplitude of the frame frequency signal; and the rest of the time is the voltage at the setting of the amplitude of the horizontal frequency signal.

1 Thus, a linearly varying signal is formed at the output of the horizontal frequency signal with a period equal to the repeat period of the lines. At the output of a frame frequency signal, a signal is generated that varies linearly over a field by a period equal to the frame repetition period. In this case, by varying the voltages on the first and second input of the switch 7, it is possible to adjust the amplitude, respectively.

45

Q tori connects to the input reference

Q

five

the voltage of the digital-to-analog converter during the synchronizing pulses of the lines is the voltage setting the amplitude of the frame frequency signal, and the rest of the time - the voltage setting the amplitude of the horizontal frequency signal.

1 Thus, at the output of the horizontal frequency signal, a signal is generated that varies linearly over a line with a period equal to the period of repeating the lines. At the output of the frame frequency signal, a signal is generated that varies linearly over the field with a period equal to the frame repetition period. In this case, by varying the voltages on the first and second inputs of the switch 7, it is possible to adjust the amplitude, respectively

horizontal frequency signal and frame frequency signal.

To obtain nonlinear voltages at the output of the first counter 2 and at the output of the second counter 5, it is possible to turn on transcoding blocks made, for example, on the basis of memory blocks. In this case, a sawtooth generator can be used, for example, as a generator of sweep signals or a generator compensating for the background of a voltage video signal.

Claims (2)

Claims 1. A horizontal frequency signal generator comprising, in series, 20 amplitudes of a horizontal frequency signal and A clock pulse generator, a first counter and a digital-to-analog converter, the output of which is a horizontal frequency signal output, characterized in that, in order to expand the functionality by additionally generating a frame frequency signal, a second counter, an inverter and a memory block are inserted Stro- The biometric input of the first counter is combined with the counting input of the second counter, with the control input of the memory unit, the inverter is connected to the reset input of the first counter n is the input of clock pulses / rows, the reset input of the second counter is the input of frame clock pulses, the outputs of the second counter connected respectively to the installation inputs of the first counter, the output of the digital-to-analog converter is connected to the input of the memory block, 5, the output of which is a frame frequency output. 2. The generator according to claim 1, characterized in that, in order to provide separate adjustment a frame frequency signal, a switch is inputted, the output of which is connected to the input voltage of the reference voltage of the D / A converter, the first and second inputs are the voltage settings of the amplitude setting, respectively, the horizontal frequency signal and the frame frequency signal, and the control input is connected to the control input of the memory block .