SU1531115A1 - Device for recognition of images - Google Patents

Abstract

The invention relates to computing and cybernetics and can be used in image processing systems. The purpose of the invention is to expand the field of application of the device due to the ability to recognize the number of images that exceeds two. Two counters, a decoder, a shift register, a memory block, two comparators, four delay elements, a second block of AND elements, five OR elements, two AND elements, a multiplexer, a second modulo two, a control unit, and a third and fourth one are entered into the device. registers. 2 ill., 1 tab.

Description

The invention relates to technical cybernetics and computing and can be used in image processing systems.

The purpose of the invention is to expand the field of application of the device due to the ability to recognize the number of images that exceeds two.

1 shows a diagram of the device; figure 2 - timing diagram of the device.

The device (Fig. 1) contains a control block 1, a generator of random numbers 2, a multiplexer 3, the first k and the second 5 registers, the first 6 and second 7 counters, a decoder 8, the first 9 and second 10 modulo two, the third 11 and the fourth 12 registers, the first 13 and second U comparators, accumulating adder 15, shift register 16, memory block 17, first l8 and second 19 And elements, first 20 and

the second 21 blocks of elements are AND, the first is 22, the second is 23, the third is 24, the fourth is 25, and the fifth is 26 elements OR, the first. 27, second 28, third 29, and fourth 30 delay elements.

The device works as follows.

Simultaneously with the Start signal, the Training signal is given to the device input. The Start signal sets the counters 6 and 7 and the adder 15 to the zero state. The signal Training through the second output of the control unit is fed to the control input of the multiplexer 3, providing communication of the block of elements AND 20 with the outputs of the generator 2 random numbers.

At the fourth output of the control unit, a sequence of pulses S is formed, which are synchronized with the moments of supply of components

..., x, x "images in persl

00

ate

the second register, and the codes of the generalized membership function (x) l of these images in the second register 5. After each pulse, the image of the training sample is fixed in the register, and the code of the generalized membership function of this image is recorded in register 5,

The number of images of each image in the training sample is equal to N, and the total mislo of images of the training sample is equal to mNjj. After each tM of pulses S, a pulse F is generated at the sixth output of the control unit. As the training sample images are fed into the accumulating adder 15, a certain value is obtained that is related to the weight of the count q. Contents accumulating adder 15 to

the power of the first 13 and second AND Comparators is compared with the numbers 0.5 (mNo - O) and 0.5 (+ O), typed in registers 11 and 12. If after presenting all the images of the training sample, the contents of adder 15 are greater than or equal to 0 , 5 (p1Mts + O), then the first comparator is triggered, if less, then the comparator is triggered /

The operation of one of the comparators causes the occurrence of 1 at the output of the fifth element OR 2b, which opens the second element I 19 at the first input, which passes a pulse F to the input. The block 17. 1 at the output of the element OR 2b opens the first element 18 and 18, which transmits a pulse F, which, having entered the input of the first counter 6, increases its contents by 1. Counter-6 counts modulo M, and its overflow pulses go to the input of the second counter 7 counting moduloip. The contents of the first counter B represent the lower bits, the second digit 7 of the counter is the high bits of the address of the memory block cell. Thus, after writing to the memory block, the address is increased by T i. .

The impulse F is also fed to the input of the random number generator 2, causing in it the generated random number TJ. In addition, the pulse F is fed to the setup input of the adder 15. The calculated weight q is compared with the threshold and, if its modulus exceeds the threshold, then the parameter L and

the sign of the weight sign g, j is written into the memory block at the address, the lower bits of which are contained in the first counter 6, and the older ones in the second counter 7. After calculating the weight q, the accumulating adder 15 is set to zero, in the random number generator is formed the new random number, and the first counter 6, if there was a recording, increases its contents by 1.

After recording the M pairs L, sign q the first counter 6 overflows, the overflow pulses are counted by the second counter 7, which overflows after recording m groups of M pairs L, sign Yats. The overflow pulse of the counter 7 is fed to the first input of the control unit 1, causing the termination of the generation of pulses S and F and the output of the signal End.

Starting from the moment of issuing at the fourth output of the pulse control unit S to the moment of the overflow of the first counter 6, the device selects features for the elementary membership function f (x). Since before the overflow of the first counter 6 the second counter 7 is in the zero state, the decoder 8 has a zero bus, i.e. bus, the number of which corresponds to the number of the elementary membership function being processed. I

The submission of each image of the training set is accompanied by the submission of the F (X) code of the generalized membership function to the second parallel register 5. If the image belongs to the j-th image, then the P (x) code contains O in the j-th position on the right, and in all the others 1. Each position of the code r (x) 3 is the code f; (x) 3 of the elementary membership function, equal to O if f. (X) +1, and 1 if fj (x) -1. Since the like outputs of the decoder B and the second register 5 are connected to the inputs of individual elements of the second block of elements 21, the outputs of which are connected to the inputs of the second element OR 23, the output of element 23 has a code corresponding to the value of x (x) +1 only when presenting images of image O, when presenting images of other images at the output of element 23, there is 1, which corresponds to the value fo (x) -1. FoCx code) to 51

given to the first input of the second adder 10 modulo two.

So, at the first input of the adder 10, fo (x) J is fed, i.e. the code of the elementary membership function), the second input is the sum of 5.1; X |, i.e. the character count ef (L, x), at the output of the adder 10, the sum fo (X;) is formed, which, according to the table, can be called the product code A f (x) Cfi (I ,, x),

those. And fo (x) ®2l; x; .

The product codes A, calculated for each image of the training sample, are fed to the input of adder 15, to the permitting input of which impulse S is received. As the images of the training sample are presented to the accumulator 15, the sum 2IA is accumulated, equal to the number of images for which the product A negatively. Since the total number of images of the training sample is mNj ,, and the number of images for which A is negative is 21A, the number of images for which fo (x) c (1, x) is positive is mNg -51Л. The weight q is the difference between the number of images for which A is positive and the number of images for which A is negative:

q tMo - from where

f (x) q) (L, x) 0.5 (tPo qO- (1

Let Γ1 j 0. Then q q | | and, if j o, then

(x) Lf (L, x) 0.5 (mNo - Q). (2)

Let q 0. Then q if (q, I b; Q, then

2: Lfo () q (i, x), 5 (mNo + o). (3)

Thus, if one of the conditions (2), (3) is fulfilled, then the modulus of the weight is greater than or equal to the threshold O and, hence, sign), i.e. its parameter L and the sign of the weight sign q must be recorded in the memory, 0.5 (mNo - Q) and 0.5 (mNo + Q) are typed in registers 11 and 12, respectively, and fed to the first inputs of the comparators 13 and II , on the second inputs of which the sum 2 fj., (x) q) is applied (1, x). The first comparator 13 is triggered when condition (2) is met, and the second comparator is triggered when condition (3) is fulfilled. Tripping any of the | parators leads to the recording of the output signal of the second comparator, equal to 15

O, if q O and 1, if q 0. Thus, in block 17 the sign of the weight q, i.e. signq. In addition, in block 17, the parameter L is also recorded that is taken from the second group of outputs of the generator 2 of random numbers.

If none of the conditions (2), (3) is fulfilled, then the recording does not take place and the sign is not included in the number M of the selected signs.

If one of the comparators has worked, then the first counter (2) will increase its contents by 1. In addition, in any case, if there is a recording or if there is no recording, the pulse F, delayed by delay element 28 and passing through the fourth element OR 25, will set the accumulating adder 15 to zero state.

Next, all nif images of the training set are presented again and the procedure described is repeated.

When such procedures are repeated in block 17, signs of C | (L, x). After fixing the M signs, the first counter 6 overflows and the pulse of its overflow enters the second counter 7. The last switch to one state causes the first output bus of the decoder 8 to be excited. Starting from this moment, the elementary membership function f (x) is processed, .. ..

In recognition mode, the device operates as follows.

Preliminary, in the fourth register 12, the number 0.5M is dialed. Start Pulse ensures that the recognizable image components are received in the register of components X | , ..., X, Xp, and in the second register 5 of the pCx code 00 ... 00. The recognition signal provides a connection between the inputs of the first block of elements AND 20 and the output of the block of memory 17. At the fifth output of the control unit, a sequence of pulses T that cause reading from block 17. Read information — the parameter L and the sign of the weight sign q are stored at the output of lock 17 until the next pulse T arrives and goes to the second group of multiplexer 3 inputs and to the third input the second adder 10. At the pen output of the adder 9, yMMa2l; Xj 1 ,,, x., Q, ..., 1, x, ® 1dHd are formed, and on b1) 1 input of the adder 10 1, X, ® sign q, which equals o

if the quantities I. sign q, are simultaneously equal to O or 1, and 1, if one of these quantities is equal to O, and the other is 1.

Thus, at the output of the adder, ra 10, a code is formed (sign q) (L, x) equal to 1 if the product (sign q) 4 (L, x) is negative, and O if this product is positive. As the pulses T are issued, the sum (sign qL,) (L, x)) is formed in the accumulating adder. The pulses T are counted by the first counter 6. The next M pulses T lead to the accumulation in the adder of the sum of 2 signji,) / (L, x) according to the M attributes of the next pattern. If this sum is positive, then the sum is 2I ((sign q) Lp (L, x L m / 2 and at the output of the second comparator I is present. O, if this sum is negative, then the sum Sl- (sign qL) 4 (L x 0.5M and the output is 1. After M pulses T, the first counter 6 overflows and the overflow pulse arrives at the enable input of register 1b, to the information input of which the code f 1 (x) is output from the output. the left bit of block 1b.

After m series of M pulses T in register 1b, a code GCxL of the generalized membership function is formed, representing the result of recognition. The overflow pulse of the second counter 7 is fed to the first input of the control unit, causing the End signal.

Claims (1)

Invention Formula The device for pattern recognition, containing the first and second registers, random number generator, accumulating adder, the first modulo-two adder, the first block of And elements, the output of the first register connected to the first inputs of the AND elements of the first group, whose outputs are connected to the inputs of the first adder modulo two, characterized in that, in order to expand the field of application of the device due to the ability to recognize the number of patterns greater than two, it contains the first and second counters, a decoder, a shift register, a block memory, the first and second comparators, four delay elements, the second block of elements And, five elements, two elements And, 0 five  , five " 0 45 Q multiplexer, modulo two second adder, control unit, flutter and fourth registers, the outputs of which are connected to the first inputs of the first and second comparators, the second inputs of which are connected to the output of the accumulating adder, the information input of which is connected to the output of the second modulo two adder, the inputs of which are connected to the outputs of the second element OR, the first modulo-two adder and to the first output of the memory unit, the second output of which is connected to the first information input of the multiplexer, the second information The input of which is connected to the output of a random number generator, the output of the multiplexer is connected to the second inputs of elements AND of the first group, the information input of the first register is the information input of the device, the information input of the second register is the control input of the device, the control inputs of the first and second registers and the first input of the third element OR is connected to the fourth output of the control unit, the first output of which is connected to the installation input of the first counter and to the first input of the fourth element and OR, the second and third outputs of the control unit are connected to the first and second control inputs of the multiplexer, the fifth output of the control unit is connected to the input of the first delay element, to the second input of the third OR element, and to the input of the memory block, the sixth output of the control unit is connected with the first input of the second element And, and with the input of the second delay element, the output of which is connected to the control input of the random number generator, with the first input of the first element AND, and with the second input of the fourth element OR, the output of the third element and the delay is connected to the first control input of the shift register and to the third input of the fourth OR element, the output of which is connected to the first control input of the accumulating adder, the second control input of which is connected to the output of the fourth delay element, the input of which is connected to the output of the third OR element, the output of the first comparator is connected to the first input of the fifth OR element, the output of the second comparator is connected to the information input of the second one the shift register, with the first information input of the memory block and with the second input of the fifth OR element, the output of which is connected to the second input of the second And element, and with the second input of the first And element, the output of which is connected to the first input of the first OR element, the second input of which is connected with the output of the first delay element, and the output is connected to the counting input of the first counter, the overflow output of which is connected to the counting input of the second counter, to the input of the third delay element and to the second control input of the shift register The ra, the output of which is the first output of the device, the output of the second element, And is connected to the input Record of the memory block whose address input 15 ten connected to the outputs of the first and second counters, the input of the decoder is connected to the output of the second counter, and the output is connected to the first inputs of the AND elements of the second group, the second inputs of which are connected to the output of the second register, and the outputs are connected to the inputs of the second OR element, the output of the random number generator is connected to the second information input of the memory block, the overflow output of the second counter is connected to the input of the Stop of the control block, the Start input of which is the Start start of the device, the Learning and Recognition of the control block are input learning and recognition device, a seventh output control unit is the second output device. I h r number ffWL    / fjy / ti. TO.ri