SU1524178A1 - A-d converter - Google Patents

Abstract

The invention relates to electrical measuring and computing equipment and can be used in information measuring systems, information transmission systems, etc. To increase speed while maintaining high accuracy of conversion, a multiplication and subtraction unit is inserted into the device, the first group of information inputs of which are connected to the group of information outputs of the register , and the second group of information inputs - to the group of information inputs of the code-voltage converter and the group of information outputs of the block Management Board. The fourth output of the control unit is the data readiness bus, and the group of information outputs of the multiplication and subtraction unit is the output data bus of the converter. 2 hp f-ly, 4 ill.

Description

The invention relates to electrical measuring and computing techniques and can be used in information measuring systems, information transmission systems, and the like.

The purpose of the invention is to improve the speed while maintaining a high conversion accuracy.

Figure 1 shows the block diagram of the converter; Fig. 2 is a functional block diagram of the control unit; FIG. 3 is the timing diagrams of the operation of the control unit} in FIG. 4 is a functional diagram of the multiply and subtract unit.

Analog-to-digital converter (figure 1) contains a switch 1,

analog storage unit 2, comparison unit 3, code-voltage converter (PKN) 4, control unit 5, register 6 and multiplication and subtraction unit 7.

Control unit 5 (Fig. 2). contains a generator of 8 clock pulses, a register of 9 successive approximations, a first inverter 10, a generator 11

trigger pulses, the first trigger 12, the second inverter 13, the second trigger 14, the first 15 and the second 16 li delay, the first 17, the second 18, the third 19, the fourth 20 and the fifth 21 OR-NK elements and the third inverter 22.

The multiplication and subtraction unit 7 (Fig. 4) contains a group of inverters 23 and an adder 24.

The Converter operates as follows.

At the beginning of the conversion cycle, the command of the control unit 5 in the analog storage unit 2 is performed

stress memorization

and (and, + li.) (k + & k),

At the second stage of the coding cycle, the process of bitwise balancing of the output voltage and the block is carried out, as a result of which the code N is set at the output of the register of the control unit 5. Its equivalent value is

II and

i.kb

+ li and

+ 2-lil +

+ 2 to Ux + 2 yy.

- the instantaneous value of the input signal; 15 - the bias voltage of block 2; - transfer coefficient of block 2; - error factor

transfer unit 2. 20 to 1 then

and and + uUft chk bk and,.

The result of the memory is received at the first descent of the comparison unit 2, where it is compared with the output voltage U. PCN4, entering the input of unit 3 of the comparison, in the process of parallel balancing. After completion of the bit balancing process, the N code from the register of the control block 5 is rewritten into register 6, in which the N code is stored until the end of the conversion cycle. At the same time, the input switch connects to the input of block 2 an output voltage of the TCH 4, equivalent to code N and equal (without taking into account the error of the PKN)

this and

whether with

where is MJ {. - displacement voltage of the comparison unit.

(

At the command of the control unit 5, the output voltage of the PCN 4 is memorized in the analog storage unit 2, on the code of which the voltage is set

and (iet + & uft) (l + uK) and, + lid + & ujt

or

and - Ux + 2uUft + 2 & К and + AUe.

in the multiplication and subtraction unit 7, the output code N of the register 6 is multiplied by two and the output code N of the register of the control unit 5 is subtracted. The output of the data block 7 multiplication and subtraction sets the code N 2n - N, the equivalent value

U5K6 2 - and .6 - Ux

five

0

five

0

five

0

five

The control unit 5 operates as follows (FIG. 3) |

From the generator output 8 clock pulses to the input of the register 9 are constantly received clock pulses. The horn 9 is in standby mode before a positive polarity start pulse is received from generator I1. When a start pulse arrives at its leading edge, the direct outputs of the first 12 and second 14 flip-flops generate a voltage of level 1. Signal level log. M from the direct output of the first trigger, which is the first output of the control unit 5, is fed to the input of the input switch 1 of the device (FIG. 2), which connects the voltage U to the input of the unit 2. The signal level log. 1 from the output of the second trigger 14 is fed to the first input of the third element OR NOT 19, at the output of which and at the output of the control unit 5, a voltage is generated at the level of the log.O, informing the consumer about the beginning of a new conversion cycle. At the same time, a start pulse through the element OR-NOT 20 and the inverter 22 is fed to the output of control unit 5 and to the second input of unit 2 for recording the instantaneous value to the block.

In addition, the trigger pulses through the fifth element 21 level log. It enters the input of the initial setup of register 9, which, if the level of the log coincides. On the course of the initial installation and the positive voltage drop of the next tactical pulse at the input of the clock pulses is set to its original state: output Qj, - level log. Oh, outputs Q, ..., Q | j, CC - level log. 1. At the end of the pulse, the recording of the voltage also ends in block 2, and the log level is set at the input of the initial setup of register 9. I and when coinciding with the positive front of the next clock pulse, the first stage of the conversion begins, consisting in equalizing the output voltage U of unit 2 with output voltage PKN 4 of the device, and at the outputs Qrt, ..., Qo. where n is the most significant bit, the code N is generated depending on the signals coming from the output of the unit 3 comparing the device to the input of the control unit 5 and accordingly to the information input of the register 9.

After the completion of the first stage of conversion, the voltage drop from the level of the log is formed at the output of the CC register 9. 1 to log level. O, which is fed through the first inverter 10 to the counting input C of the first flip-flop 12, as a result of which the forward output of the latter is set to a log level. A. This signal is fed to the output of control unit 5 and, accordingly, to the input of the input switch 1 of the device, which connects the output of the PKN 4 to the input of the unit. Level log. From the direct output of the trigger 12 is fed to the first input of the first element OR NOT 17 to the second input of which the signal delayed by the first line 15 of the inverse output of the trigger 12 arrives. If the levels of the log.O match on both inputs of the element OR NOT 17 on it the output is formed by a pulse level log. 1, which through the quarter element OR-NOT 20 and the third inverter 22 is fed to the output of control unit 5 and, respectively, to the second input of unit 2 for recording the voltage and, coming from the control terminal PCN 4. Simultaneously, the pulse and voltage from the output of the first element OR- NOT 17 is fed to the output of the control unit 5 and, accordingly, to the control input

0

register 6 of the device for writing the output code N of the register 9 of the control unit to the register 6 of the device. In addition, the pulse from the output of the OR-NOT 17 element goes to the first input of the second element SH-NOT 18 and through the second inverter 13 and the second delay line 16 to the second input of the OR-0 element 18. This ensures the formation of the second element Rra4iE 18 at the output impulse of positive polarity, the beginning of which coincides with the end of the impulse at the output of elecmentiona 17. The impulse formed through the fifth element OR-NOT 21 log level. It arrives at the input of the initial setup of register 9. Register 9 is reset to the initial state with the arrival of a positive front of the next clock pulse at a log level. About at its entrance initial setup. After the end of the pulse on this input of the register,

 logging level is applied. 1 and with the arrival of the positive edge of the next clock pulse, the second transformation stage begins. At the same time, by a positive drop in its pulse at the output of the second delay line 16, the second flip-flop 14 is tilted, at the forward output of which a log level is set. O. After the end of the second stage

5 conversions at the outputs .., the Qo of the register 9 forms the code N, and at the output of the CC of the register 9 and respectively at the second input of the third element OR NOT 19 is set

0 level log. A. If the levels of the log are the same. On the two inputs of the third element OR NOT 19 at the output of the latter and at the output of the control unit 5 a level log is set,.

5 1, indicating to the consumer the availability of reliable data at the output of the device data.

Block 7 multiplication and subtraction 0 provides automatic multiplication by two codes N, arriving at the first group of information inputs, and subtracting code N, arriving at the second group of information inputs; 5 dov. Multiplication by a given N code is provided by shifting the code. N one unit to the right (in the direction of the older bits). To perform the operation of subtracting the 2N and N codes on the adder 24, the code N must be converted into an additional code. The conversion of the N code into the additional code in the multiplication and subtraction block 7 is carried out as follows. The N code is pre-inverted by a group of inverters 23, and the low-order unit is added to the result N by a constant connection to the input

nose RD adder 2A level log. M.

Claims (3)

Invention Formula 1. An analog-to-digital converter containing an input switch, the first information input of which is an input bus, the second information input connected to the code-voltage converter output, the control input to the first output of the control unit, and the output connected to the information input of an analog storage unit, the control input of which is connected to the second control unit output, and the output connected to the first input of the comparator unit, the second input of which is connected to the output of the code-voltage converter, and the output connected to the input of the control unit, the register whose group of informational inputs is connected to the information output of the control unit, the third output of which is connected to register input, so that, in order to improve speed while maintaining high accuracy of conversion, a multiplying and subtracting unit is inserted into it, the first group of information inputs of which are connected The group of information outputs of the register, the second group of information inputs are combined with the corresponding inputs of the code-voltage converter and connected to the group of information outputs of the control unit, the fourth output of which is the data readiness bus, and the group of information outputs of the multiplication and subtraction unit by bus. 2. The converter according to claim 1, T is characterized in that the control unit is executed on a clock pulse generator, a sequential approximation register, a trigger pulse generator, three inverters, two triggers, two delay lines 0 50 five 0 5 0 5 0 five Five elements of the STI-NOT, the first input of the first of which is the first output of the block and is connected to the forward output of the first trigger, the inverse output of which through the delay line is connected to the second input of the first OR-NOT element, the output of which is connected to the first inputs of the second and The third element OR NOT is the third output of the block and through the first inverter and the second delay line is connected to the second input of the second element OR NOT and to the C input of the second trigger, whose D input is a common bus, the S input is combined with the entrance of the first trigger a, the second input of the third and the first input of the fourth element OR NOT and connected to the generator output, start triggering, the output of the second trigger connected to the first input of the fifth element OR NOT, the output of which is the fourth output of the block, and the second input combined with the input second in- I vertor and connected to the end output the cycle of the sequential approximation register, whose information input is the input of the block, the input of clock pulses is connected to. the clock pulse generator output, the initial setup input — with the output of the fourth element OR — NOT, and the data outputs are a group of information outputs of the block, while the output of the second and scherter are connected to the C input of the first trigger, the D input of which is common bus, and the output of the third element OR is NOT connected to the input of the third inverter, the output of which is the second output of the block, and the output of the second element OR is NOT connected to the second input of the fourth element OR NOT. 3. The converter according to claim 1, characterized in that the multiplying and subtracting unit is made on a group of inverters and an adder, the first inputs of which are the first group of information inputs of the block, the second inputs are connected to the outputs of the corresponding inverters group, the inputs of which are the second the group of information inputs of the block, and the outputs of the adder are a group of information codes of the block. Wil 8 L / l 7 / {mpusi Sux.t2 22 Outlet L / х7 / g .20  GL / X5 "a S (a-i) f h I b / fle And% 5 Bi / xKQ Ex 15 Bt / x.Jf BM.JS vy-18 OUT.1H &, 1st Awtkt ewrit / J (I, ... A / AM # / fieL