SU1522206A1 - Device for dynamic priority - Google Patents

Abstract

The invention relates to discrete automation and computing, can be used to organize the priority service requests. The purpose of the invention is to expand the field of application of the device by taking into account when determining the priority of the time spent in the queue for service requests. The device contains a synchronization unit 1, a priority increasing block 2, a priority analysis block 3, initial setup inputs 4, priority code inputs 5, request inputs 6, request clearing inputs 7, request confirmation outputs 8, OR NOT element 9. The synchronization unit generates pulses of tact and interrogation, arriving at priority increasing blocks, in which then, taking into account priorities and time spent on queuing for servicing, the pulses are generated. These pulses arrive at the inputs in a certain way selected elements of the delay of the priority analysis block, as a result only one trigger of the priority analysis block is transferred to the single state. The column of the priority analysis block, in which the trigger is in a single state, indicates that at a given moment of time it is necessary to maintain the priority direction assigned to this column of the priority analysis matrix. 4 il.

Description

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The invention relates to discrete automation and computing, can be used to organize the priority service of requests.

The purpose of the invention is to expand the scope of application of the device by taking into account when determining the priority of the time when requests are in the service queue.

Fig. 1 shows a block diagram of the device I in Fig. 2 a block diagram of the syncronization block | in FIG. 3, a block diagram of a kara-block. priority clearing; Fig. 4 of the structure of the analysis block of priorities.

The device contains a block of 1 synchronized

Tzadik, blocks 2, -2 „Increasing the priority of which, at limited intervals of thetates, the priority analysis block 3j - the group of inputs of the initial installation 4 4, the group of inputs of priority codes

query input group

a group of inputs for removing requests 7., r7n a group of outputs for confirming requests for a bc-bp element OR-NOT 9, output 10 of the element SHY-NOT, outputs 11, 12 of the synchronization unit.

The synchronization block contains the element And 13, divider 14, the generator 15 clock pulses

Priority override block contains divider 16, counter 17, group

25

thirty

In time, impulses arriving at the counting -inputs of summations appear.

Counters: with sequential carry 17c,. Pulse Frequency to Summing Meters 17i-17

. Depends on the set division factors of dividers, frequency 1b ,, - 1b at a constant frequency of impulses received from the generator of i-spools G5, In counters; 17, these pulses are summed up, as a result of which the outputs of the counters 17. (17, appear with the potentials arriving at the corresponding first inputs of the E-18 unit). Since initially to:

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elements and 18, the decoder 19, the register of the device outputs 8, -8 are missing .20, the exit attribute of the removal request 21, the group of information outputs of the block

I 22, -22 „element And 23, trigger 24.

I The priority analysis block contains

I L trigger groups 25, -25p „(1 1 L),

i N elements of ШШ ,,, Ь groups of elements И 27 ,, - 27е „, Ь groups of delay elements 28,,

The proposed device works as follows.

When the power is turned on, all the triggers 24 (24, counters, register 20, -20f, triggers 25 of the priority analysis block 3 are set to the initial (zero) state by signals received at the corresponding inputs, 4.4p, and outputs 21, -21, where tt - the number of serviced priority

I. directions J am - priority register size.55

After that, priority codes are abo-. If the inputs coming through the groups of inputs are written to the corresponding potentials due to the fact that all triggers of the priority analysis block are in the zero state, then the output of element 9 will not have a low potential. The resolution potential from the output of the SHSh-NOT 9 element on the .10 output enters the synchronization unit 1 and is present at the second input of the element. And the 13th synchronization unit 5. 1, Divide frequency 14 produces the frequency division of the generator 15, resulting in a certain time interval at the output of frequency divider 14, a pulse appears that passes through the currently open element 13 and enters output 12 of the synchronization unit 1, This the impulse is then passed through the output 12 of the block 2, arrives at the second inputs of the elements And 18, thereby permitting the reading of information from the counters 17, -17 to the decoders 19h-19. After decrypting this information on one of. 1 outputs

priority registers of 20, -2Qp for each priority direction, in

The result is that dividers, clocks with a variable division factor are adjusted to the specified division factors. The fact of a request from subscribers is identified with the appearance of signals by, inputs .., as a result of which the corresponding triggers (are transferred to the single state. The potential from the single output of the triggers is sent to the first inputs

 TOV. And, thus permitting. The arrival of pulses from a pulse generator 15 at input 1.1 through

the elements And 23 / - 23p, .counting; divider inputs, at the output

which o.defined intervals

In time, impulses arriving at the counting -inputs of summations appear.

Counters: with sequential carry 17c,. The frequency of incoming im-: pulses in summing counters 17i-17n

. Depends on the set division factors of dividers, frequency 1b ,, - 1b at a constant frequency of impulses received from the generator of i-spools G5, In counters; 17, these pulses are summed, as a result of which the outputs of the counters 17. (17, the potentials appear at the corresponding first inputs of the E-elements of block 18). Since initially on:

device outputs 8, -8 are absent

the potentials due to the fact that all the triggers of the priority analysis block, are in the zero state, then the output of element 9 will not be low potential. The resolution potential from the output of the SHSh-HE 9 element at the output of .10 enters the synchronization unit 1 and is present at the second input of the element. And the 13th synchronization unit. 1, Divide the frequency of 14 trans. The frequency division of the generator 15, resulting in a certain time interval at the output of frequency divider 14, a pulse appears that passes through the currently open element And 13 and arrives at output 12 of synchronization unit 1, This pulse, then passes through the output 12 blocks 2, arrives at the second inputs of the And 18 elements, thereby permitting the reading of information from the counters 17, -17 to the decoders 19h-19. After decrypting this information on one of. 1 outputs

descramblers appear pulses under the condition that there is a request in the corresponding block 2, which then outputs 22 to the inputs of the priority analysis block 3. Arrivals to the outputs 22 of the priority analysis block 3, these pulses arrive at the inputs of the delay elements 28 The delays 28 of the priority analysis block 3 are determined from the relation: t ,, - j it + tg, where t is the response time of the trigger matrix analysis of priorities 3, j 1,1, i. - l, n t is the total response time of the elements OR 26, YLI NOT 9 and element AND 27. Due to such delays, increasing from left to right and from top to bottom in the priority analysis block 3, occurs. transfer to one state of only one trigger 25 of the priority analysis block 3. As a result, the potential appears at its single output

Which passes through the corresponding 25K th priority building block,

the element OR 26, and appears on the same input of the launch of which is connected to the KM

from the outputs of device B, - This is by the potential input of the device request, the first one testifies to the fact that this synchronization unit is connected to

point in time must be serviced by the synchronization inputs of blocks of increasing30

This is the priority direction, at the corresponding output of which there is a resolving potential. The zero potential from the output of the element ORI- NE 9 is applied to the third inputs of elements AND 27 of the priority analysis block 3, which prevents all the other triggers of the priority analysis block 3 from transitioning to the unit state. In addition, the same inhibitory potential from the output of element 9 enters the input element And 13 of the synchronization unit 1; As a result, the element And 13 is closed and the pulses from the divider 14 are not received in the blocks 2. For the stable operation of the priority analysis block 3, it is necessary that the pulse period from the divider 14 be longer than the maximum delay present in block 3, i.e. . n-l t + t. At the same time

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 3ij max mesh on the appearance of signals on the neighbor- JQ

The delay elements 28 of any line of the priority analysis block 3 will move the trigger with a lower sequence number faster to a single state due to a smaller delay of the same name.eg the sign of the withdrawal of the K-th block request By inhibiting potential from zero increase in priority is closed from the output of this trigger an elec- tric K input of the reset of the analysis block, an AND 27 adjoining trigger with a large sequence number, as a result of a priority pony, the K-th output of the priority analysis block. connected to the K-m output request confirmation and with the K-m input of the element ORI, whose output is connected to the lock input of the synchronization block, characterized in that, in order to expand the field of application of the device by taking into account when determining the priority of the time spent in the service queue, the output of element I -OTi-HE is connected to the blocking input of the priority analysis block, the second output of the synchronization block is connected to the resolution inputs from issuing the priority of the priority scaling blocks. The K-and device-request-release input is connected to the input of the initial installation of the K-th priority builder, whose information output group is connected to. K-and a group of inputs of the priority analysis block; K-th input of the initial installation of the device connected to the priority fixation input of the K-th priority analysis block; output

priorities, with each priority increment block containing a register.

The potential is only at one of the outputs of the device.

Upon completion of the request service, each block 2 receives a signal on input 7 to the zero input of trigger 24, which flips it to the zero state. The same signal zeroes the counter 17 and the trigger column of the priority analysis block 3, corresponding to the given priority direction. As a result, the element And 13 of block 1 opens and the device operation cycle repeats ...

Claims (1)

Invention Formula Q Dynamic priority device containing N blocks of incrementing priority (Y - number of subscribers), priority analysis block, synchronization block, OR-NOT element, the K th input of the priority code (K 1, N) of the device connected to the information input 0 five 0 Q the sign of the removal of the K-th priority request block is connected to the .K th reset input of the analysis block Neither priority, K th output of the priority analysis block. Connected to the K th output of the device request confirmation, and the K th input of the element OR, whose output is connected to the lock input of the synchronization block, characterized in that, in order to expand the area use of the device by taking into account when determining the priority of the time spent in the service queue, the output of the I-OTi-HE element is connected to the blocking input of the priority analysis block, the second output of the synchronization block is connected to the enable inputs from the priority block output CAPACITY priorities. The K-and device-request-release input is connected to the input of the initial installation of the K-th priority building block, the group of information outputs of which is connected to. K-and a group of inputs of the priority analysis block; K-th input of the initial installation of the device connected to the priority fixation input of the K-th priority analysis block; output the sign of the removal of the K-th priority request block is connected to the .K th reset input of the analysis block priorities, with each priority increment block containing a register. divider, counter element group AND decoder, first element I and first trigger 5 and the input of the initial setting of the priority increment block is connected to the input w of the installation in O of the first trigger and counter, the counting input and outputs of which are connected respectively to the output of the divider and the first inputs of the elements And the groups, -jg, the second inputs of which are connected to the input of permitting the issuance of priority of the block, the input of latching the priority of which is connected to the input of the register entry, the informational input and output of which i are connected, respectively, and formation; On one input of the extension unit, the information input of the divider e whose counting input is connected to the output of the first element I, the first 0 and the second inputs of which are connected respectively to c. the output of the first trigger and the input of the sync module and the priority incrementing block, the start input of which is connected to the input of the 25 in 1 setup of the first trigger g of the outputs of elements AND of the group are connected to the information inputs of the decoder, the group of outputs of which is the information output group of -sf) of priority, the priority analysis block contains S groups of L trig ger (L is the number of inputs in each group of information inputs of the device) the first group of L-1 elements. delays, groups of L delay elements, the first group of L-1 HS elements of N – i groups of L elements And, g N elements OR, the M th input (, LI) of the first group of information inputs of the priority block is connected to the input of the M th delay element of the first group, the L th input of the first group of information inputs of the priority analysis block is connected to the installation input of 1 L- ro the trigger of the first group, the reset input of the priority analysis block is connected to the installation inputs of the K th group triggers, the blocking input of the priority analysis block is connected to the first inputs of the AND elements of all groups, the output of the Mth delay element of the first group is connected to the second input of M- that element a -and the first group, the third input of the M-th element AND of the first group is connected to the inverse output of the (M + 1) th trigger of the N-th group, the output of the element AND of the first group is connected to the input of the installation in 1 trigger of the first group, direct output (, L) trigger of the K-th group is connected to the P-th input of the K-th element OR, the output of which is connected to the K-th output of the priority analysis block, P-and the input of the A-th group (, N) of the information inputs is connected to the input - the house of the element Zadeh, rzhki A-th group, the output of which is connected to the second input of the P-th element I. A-group, the output of which is connected to the input set ki 1 Pm trigger the k-th group, the inverse output of the first flip-flop F i-th group (, N-1) is connected to the third input P th element and (i + l) and the group. l / f.z f2 fih Sn 72 ti 2211 71, 22 (z 72 „72ii 71 g FigL atr j ia fn2ff7