SU1520506A1 - Device for comparing numbers - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to compare numbers in the binary classical number system, P-codes and optimal P-Fibonacci codes, the minimum, optimal, batch, batch-optimal forms of images in the binary redundant number system. The invention allows to extend the functionality due to the ability to compare numbers in various forms of images of the binary redundant number system and P-Fibonacci codes. The device contains in each bit a one-bit comparison circuit 1, the elements OR 2 and 12, the elements AND 3,5,6,7,8,9,11 and 14, and the elements NOT 4,10 and 13 with corresponding links. 2 Il.

Description

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The invention relates to computing and can be used to compare numbers in P-codes and optimal P-Fibonacci codes of minimum, optimal, batch, batch-optimal forms of images in a binary redundant t-counting system.

The purpose of the invention is the expansion of functional-genal capabilities due to the ability to compare numbers in the minimum, optimal S packet, packet-optimal forms of the binary redundant number system while maintaining the possibility of comparing Fibonacci codes.

FIG. 1 shows a bit pattern for comparing numbers; FIG. 2 is a diagram of a one-bit comparison circuit.

The device bit (Fig. T) contains a one-bit comparison circuit 1, the main element OR 2, the dc main element FROM, the first element NOT 4, the first and second additional elements AND 5 and 6, the fourth additional element AND 7, the third and sixth, additional elements H 8 and 9, the second element. NOT 10, fifth additional element AND t1, additional element OR 12, third element NOT 13, seventh additional element AND tA ,, direct and inverse inputs 15 and 16 bits first

device number; direct and inverse inputs 17 and 18 bits of the second number of the device; eighth additional element I 19; fourth input 20 specifying the device mode, first to third inputs 21-23 setting the device mode, signal outputs 24 and 25 The first and second groups of the device are the input 26 of the resolution and the output 27 Equals to the comparison circuit 1.

The one-bit bottom comparison circuit 1 (Fig. 2) contains the first and second AND-HE elements 28 and 29 and the AND 30 element, with input 26 connected to the first inputs of the AND-NE elements 28 and 29, the outputs of which are outputs 24 and 25 of the circuit 1 and are connected to the inputs of the element 30, the output of which is the output 27 of the comparison circuit 1, the input 26 of which is connected to the third input of the element 30, inputs 15 and 18 are connected respectively to the second and third inputs of the element J – J 29, inputs 16 and 17 - respectively, with the second and third inputs of the element AND-NO 28,

The known binary t-system is numbered.

V. (i) 0pri i О

1 about i - t

(ABOUT

i-n

 % Vt (i-t-j) with i - 7 t, where t is 0,1,2,3. ,,,.

When we obtain a row of binary ti number systems;

1 1 2 2 3 4 5 7 9 12 16 21 28 37 49,., (2)

In the binary t-number system it is possible to represent numbers in several forms of images.

| In the binary t-number system, any natural A can be represented in a bidet

L i: a; h, (i), where a,, (3)

B. The minimum form uses combinations of decomposition (3), in images of which, in general, after a single digit of discharge there should be at least four zero. . Such combinations contain the minimum number of units.

The power of the minimum code is η / (n + 1). In the optimal form, the coefficients a. polynomial (3) are determined from the condition

P

0priF (p-1) A- X ,, (p)

1priflp-1) 4A- 1 (k), (4)

where, (n) O with n 0

| (n-t-j) -f1 with n O, j, (n) is the optimal power

code that

A characteristic feature of optimal images is that the two adjacent units have at least t and no more than 2t zeros.

Any number in the packet form of images can be represented as

A 110.,. 011 ,,. 0110, .. 0110.,. 0

t.

m

k-1

nik

The batch code has the following properties:

power M (n)

the number of zero characters n. P: / 3 (j 1, k-1). Any number

V, (n + 3), m

O.nj B

can be written in batch optimal

form as

J

.0110, ... 11Ch..0 I, BOS

lt

Batch-optimal code has the following properties:

power M (n) (f, (n + 1), the number of zeros between packets

 lT3i r b2.

The device allows you to compare the Fibonacci code and the optimal code for any natural number t p, and the minimum, batch, batch-optimal codes are only for.

An analysis of the properties of the minimum, optimal, batch, batch-optimal forms of images in the binary t-numbering system allows us to conclude that if the numbers to be compared in the i-th bit are equal and have a single state, then for the minimum form of images, comparing bit (x-5) -th (this is due to the fact that in the minimum form the number of zeros between units 4), for the optimal form1F1; images of the binary t-number system, the optimal Fibonacci (it-1) th, (t p) bit, for the batch form # 1, if the high bit of the packet, then (1-1) -th, if the youngest, This is (x-4) -th bit, for a batch-optimal one, if the high bit of a packet is (1-1) -th bit, if a low-order (1-2) th bit is subjected to a comparison operation.

Input 20 serves to organize

comparison operations in the minimal form of the image of numbers.

Input 21 serves to organize the comparison of numbers in the P-Fibonacci code, in the optimal P-Fibonacci code, the optimal form of the images of numbers in,; binary t-number system.

Input 22 serves to organize the comparison of the packet form of the images of the number J to compare the numbers in the binary classical number system.

The input 23 is slulit for arranging a comparison in the packet-optimal form of images in a binary redundant number system.

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15

20

25

thirty

35

40

45

50

55

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The device (Fig. 1) works as follows.

When comparing P-codes and optimal Fibonacci P-codes, as well as the optimal form of images of the binary redundant number system (provided that the compared i bits are equal and single), a single signal appears at the output 27 of the single-bit comparison circuit 1 ix bits , the input to the input element And 3, since the numbers in the considered discharge are equal and single, at the input 16 there is a zero potential, which closes the element And 3 and leads to the appearance at the output of the element NOT 4 a single signal, the latter arrives at the input element a AND 5, and if at the input 21 there is a comparison resolution signal in the considered forms, then at the output of element 5 there is formed a single signal arriving at the input of element ШВ1 2 (i-2) -ro bit and allowing comparison of numbers in (i- 2) -x bit dah.

If, however, the bits are equal and have a zero value, a single signal is also generated at the output 27, which, if there is a signal from the OR 2 output and a single signal from the inverse output 16, generates a single output signal that locks through the HE element 4 And 19, 5, 6.8 and allowing polling of the next minor (il) -ro device bit.

When comparing numbers in the minimum form of images, the device works in the same way, only the signal permitting comparisons from the output of the element AND 19 at equal unit bits is fed to the input of the element OR 2 (i-5) -ro discharge.

When comparing the numbers in the batch form of images, the control signal is fed to the input 22. At zero i-ro bits, the comparison process proceeds in a similar way. With equal unit bits, the unit signal is formed at the output of the element And 6, and if at the second input there is an ele. And 7 there is a logical unit, indicating that the previous (1 + 1) -th bit contains the unit values of the first and second numbers, then at the output of the And 7 element, a signal is generated that arrives at the input of the element OR 2 (i-4 ) -ro bit, if the second input of the And 7 element is a logical zero, then a single signal is output at the output of the And 11 element, arriving at the input of the OR 2 (il) -ro bit element.

When comparing numbers in the batch-optimal form of the image, the control signal is fed to the input 23 and the comparison process proceeds similarly to the comparison process in the batch-shaped image, and only if there is a single signal at the second input of the element And 9 the signal from the output of the element | ; OR 2 (i-2) -ro bit. When comparing numbers in the classical binary number system, a single signal is fed to input 22 or input 23, to the second inputs of elements 7 and 9, a constant zero is applied, which means that single equal high bits are not considered high in iM bits. unit bits of the packet, and the signal is fed to the input of the next least significant bit. For the convenience of this comparison operation, it is advisable to connect the first code of another AND element to the output of the OR t2 element, to the second input of which a logical unit would be supplied when comparing in batch and batch-optimal forms of images and a logical zero when comparing and the output would be the corresponding output.

in the device at t О, the comparison proceeds in the classical binary number system through the output of the element And 5 with a single potential band at the input 21.

It should be noted that the implementation of the comparison in the reduced forms of the redundant numbering system takes place significantly more than in the binary classical numbering system.

Claims (1)

Invention Formula A device for comparing numbers, containing in the i-th bit (, n is the number of digits in the number) a one-bit comparison circuit, in each bit, except the first, the main element of each bit, except the n-th, the main element the first and second informational inputs ten 15 20 25 -,, 5205068 a one-bit comparison circuit of the i-ro bit of the device is connected respectively to the direct and inverse inputs of the i-ro bit of the first number of the device; the third and fourth information inputs of a single-bit comparison circuit of the i-ro bit of the device are connected to the direct and inverse inputs The i-ro bit of the second device number, the inverse outputs of the Smaller and More one-bit comparison circuit. The i-bit device bits are the i-th signal outputs of the first and second groups of the device, respectively, whose start input is connected to the input The resolution of a one-bit device comparison circuit of a device bit, direct output is equal to the one-bit device comparison circuit of a first device bit output is equal to a device, the main element rover And the device’s i-ro bit are connected to the primary input of the main element OR (i- t) -ro device bit in each iM bit, except for the n-th device, the output of the main element OR. connected to the resolution input of a one-bit comparison circuit; in addition to the first one, the resolution input and the second information input of the one-digit comparison circuit are connected respectively to the first and second inputs of the basic JHoro element AND, differ 35 0 0 five  functional capabilities due to the ability to compare numbers in the minimum, optimal, packet and packet-optimal forms of the binary redundant number system while retaining the ability to compare Fibonacci codes, each i-th bit, except the first, contains first to third elements NOT from the first to the seventh, the additional element is Wi AND, each i-th bit, except for the first and second device, contains an additional element OR, each i-th bit of the device, except the first, second, third and fourth contains the eighth additional element And, and in each i-th bit, except the first, the device is a direct output Equal to a one-bit comparison circuit is connected to the third input of the main element And, whose output is connected to the input of the first element NOT, the output of which is connected to the first inputs of the first, second and third additional elements And, the second inputs of which are connected respectively to the inputs from the first to third settings of the device mode, the output of the second additional element And connected to the first inputs of the fourth and fifth additional elements And, output the fourth additional element And through the second element NOT - with the second input of the fifth additional element I, the output of the third additional element ll - with the first inputs of the sixth and seventh additional AND gates, the output of the sixth AND additional element via a third element not - to a second input of the seventh AND additional element, in each i-th discharge, except the first and second device outputs the second and third additional elements and are connected respectively, the first and second inputs of the 25 5) th device, the output of the additional element OR, in each iM bit, except from the first to the fourth, the device, the output of the first element NOT and the fourth input of the device mode setting are connected respectively to the first and the second ten 2050610 the inputs of the eighth additional element And, the outputs of the fifth and seventh additional elements AND i-ro bit of the device are connected respectively to the second and third inputs of the main element OR (il) -ro device bit, the output of the first additional element And i-ro bit of the device connected to the fourth input of the main element OR (itl) -ro (, 1 ... is the number system parameter) of the device bit, the output of the sixth additional element AND i-ro device bit is the fifth input of the main OR element (i- 2 ) device bit output, quarter output the first additional element and i-ro discharge device - a sixth input of the main cell Hilti (i- 4) th discharge device, the output of AND eighth additional i-ro discharge device - a seventh input of the main cell OR (i15 20 the complementary element OR i-ro device bits - with the combined second inputs of the fourth and sixth additional AND elements (device bits.