SU1510090A2 - Delta-modulator - Google Patents

Abstract

The invention relates to automation and computing, and is an improvement to the device in an. N 1448411. Its use in digital signal processing devices allows widening the range of possible applications by generating an output signal in a multi-level delta modulation format with switchable quantizing characteristic. The delta-modulator contains a comparator 1, a controlled inverter 2, a generator of 3 clock pulses, a comparator 4 characters, a reversible counter 5, an encoder 6, a digital-to-analog converter 7, a driver of 8 pulses, triggers 9, 14, 15 element 11, delay element 12, element 13 and element EXCLUSIVE OR 16. The goal is achieved by introducing a reversible counter 17, a code setting unit 18, a divider 19 with a programmable division factor and delay elements 20, 21. 3 ill., 1 tab.

Description

SP

WITH

0t / eJ

M

31510

The invention relates to automation and computational techniques, and can be used in digital signal processing devices and is an improvement on the device by the author. No

The purpose of the invention is to expand the area of possible application by generating an output signal in a multilevel delta modulation format with a switchable quantizing characteristic.

FIG. 1 is a functional diagram of a delta modulator; FIG. 2 - execution of the encoder; in fig. 3 - time diagrams of work.

The delta-modulator contains the first comparator 1, a controlled inverter 2, a generator of 3 clock pulses, a second comparator of k characters, a first reversible counter 5, an encoder 6, a digital-to-analog converter 7, a driver of 8 pulses, the first counting trigger E, an element BAN 10, element 11, first delay element 12, element OR 13, second 14 and third 15 D-flip-flops, element EXCLUSIVE OR 16, second reversible counter 17, block 18 task codes, divider 19 with a programmable coefficient; second 20 and third 21 delay elements. In FIG. 1, the first 22, second 23, third 2k, fourth 25, and fifth 5b outputs are indicated.

The encoder 6 contains (Fig. 2) element And 27, the elements of the prohibition 28 and 29,

The divider 19 can be made in the form of a counter with switchable coefficients.

The recalculation center, when the outputs of the counter bits are connected via a switch to the counter zeroing input.

FIG. Figure 3 shows the signals appearing at the outputs of the respective blocks, with the symbols of Figures 1 and 3 coinciding.

The delta modulator operates as follows.

The input signal U (, (t) is fed to the input. Control (th inverter 2 and the sign comparator input. Comparator k generates output signals according to the rule

Go, U ,, (t) 0,

  B, which are control for unit 2. Control inverter 2 axis

0 5 0

There is a rule for converting the input signal.

and ujt) and oh

five

0

five

0

five

V I ujt), U4 1

those. the output of block 2 is always non-negative.

Signal,. the value of which does not exceed the interval about, and ", where C is the nominal voltage of the delta modulator, from the output of the inverter 2 is fed to the input of the comparator 1, the second input of which receives the feedback voltage from the converter 7. If the signal of the converter 7 is less than the signal), the positive pulse of the comparator 1 permits the passage of the clock pulse of the generator 3 through the encoder 6 to the input of the addition of the first reversible counter 5. If) and (c), then the output impulse of the generator 3. Through the encoder 6 enters the subtraction input of counter 5, and this leads to a reduction of feedback signal from the converter's signal 7. Thus, when u c e iZ, the communication signal U- follows the signal U, and the signal at the first output of the encoder 6, which fixes the maximum state of the counter 5, is absent. At the output of the element BAN 10, a signal is generated that corresponds to the output signal of comparator 1, which through the element OR 13 enters the information input of the trigger 14, since the signal at the output of the element 11 also is absent. The delay element -12 is necessary for matching the speed of the blocks 1, 6 and 7 and delays the clock signals of the generator 3 by the time t s, where t is the speed of the blocks 1.5–7.10 and 13. The trigger 14 performs the function of the zero-order locking circuit .

The trigger 15 is necessary for fixing the state of the output signal of the comparator 4, which is provided by the clock pulses of the generator 3, and also controls the operation of the element 1b. The output signal of the trigger 15 is fed to the input of the element EXCLUSIVE OR 16, as a result, the signal at the output of the latter at zero

trigger state 15 (U

1510090

in

decay Ug (t)

on the contrary,

Corresponds to the output signal of the trigger 1, with a single (U -c 0) - inverse output signal of the trigger 1.

Thus, the signal at the output of the EXCLUSIVE OR 1b element corresponds to an increase in the approximating voltage of the converter 7. At the same time, if the input signal monotonously increases, a delta sequence is formed at the output of element 1b, which is the first output 22 of the delta modulator, than zeros. With monotonous, this ratio is in the area where

the slope of the input signal is close to zero, the number of ones and zeros in the sequence at the output of element 1b is approximately the same. At the output of the trigger 15 and the outputs of the reversible counter 5, the second 23 and third 2k outputs of the delta modulator, an output signal is generated in the pulse code modulation (PCM) format, represented by a direct code with a sign digit.

If b is equal, the output pulses of the generator 3 through the encoder fill up the reversible counter 5, as a result of which the converter 7 produces the value U-, and the third output of the encoder 6 has a pulse that prevents the signals of the comparator 1 from passing through the element BAN 10, and allows the passage of the pulses of the trigger 9 through the elements AND P. And OR 13 to the input of the trigger 1. Before the appearance of the specified pulse on the third output of the encoder 6, the trigger 9 operates in the counting mode, changing after the arrival of each clock pulse from the output of the blinker ka 3 on its opposite state. The pulse at the third output of block 6 through the front-edge driver 8 sets the trigger 9 to a single position, thereby eliminating errors in the output code due to incorrect phasing of the output pulses of the trigger 9.

When / Ug, f Itz, the pulse from the output of the generator 3 does not change the state of the reversible counter 5, since the encoder 6 blocks the passage of the clock pulses to the tracking input of the counter 5 when it is completely filled.

ten

0) COOT- At the same time, the pulse from the output of generator 3 will change the state of trigger 9 to zero. Therefore, in case of When the input signal raises the nominal value Uj, the delta modulator, the output of element 1b will form a code — a sequential sequence of ones and zeros corresponding to the U sign. Thus, at the first output 22 of the device, a one-bit delta sequence is formed that corresponds to the input signal, which is In the interval C, UH C, on the second 23 and third outputs, an PCM signal is generated corresponding to the sign and module of the approximating signal in the specified range. Wherein

20 signals are formed at the outputs with

repetition rate determined by the sampling rate for linear delta modulation. If the input signal is outside the f-U interval, U, by

In the first output of the delta modulator, an alternating sequence of ones and zeros is formed, corresponding to 15

35

40

to the limit / Up (Uj ,, and on the second and third outputs - a signal in the form of 2Q PCM, equal to the given limit.

The operation of the encoder 6 is completely analogous to the operation of the block of the same name known, understood from the one shown in FIG. 2 is a functional diagram and does not need to be explained.

The signal generation in the multilevel delta modulation (MDM) format at the outputs of the second reversible counter 17, which are the fourth outputs 25 of the device, is carried out as follows.

The one-bit code U, is fed to the input of the addition / subtraction of the reversible counter 17, to the counting input of which through the delay element 20 the clock pulses arrive. Time

 io „„

the delay of the signal t j in element 20 takes into account the speed of the trigger I and element 16 and must be greater than the time it takes for the signal to pass through these blocks.

The divider 19 provides a frequency division of the clock generator 3 with a programmable conversion factor. ,,:, i ;, Td / T „d ;, where Td and, n are the sampling rates at linear and multilevel

45

50

55

510090

- If you go with it, you can always play

five

0

to the limit / Up (Uj ,, and on the second and third outputs - a signal in the format QM PCM, equal to the given limit.

The operation of the encoder 6 is completely analogous to the operation of the block of the same name known, understood from the one shown in FIG. 2 is a functional diagram and does not need to be explained.

The signal generation in the multilevel delta modulation (MDM) format at the outputs of the second reversible counter 17, which are the fourth outputs 25 of the device, is carried out as follows.

The one-bit code U, is fed to the input of the addition / subtraction of the reversible counter 17, to the counting input of which through the delay element 20 the clock pulses arrive. Time

 io „„

the delay of the signal t j in element 20 takes into account the speed of the trigger I and element 16 and must be greater than the time it takes for the signal to pass through these blocks.

The divider 19 provides a frequency division of the clock generator 3 with a programmable conversion factor. ,,:, i ;, Td / T „d ;, where Td and, n are the sampling rates at linear and multilevel

five

0

five

 1510090

delta modulations, respectively, with Td,. The value of lu can be either even or odd.

It is assumed that at time o, (Fig. 3) a certain value of the multi-level code at the outputs of counter 17 has already been formed, as evidenced by the presence of a pulsed signal U at the output of divider 19, the conversion factor of which is even and is, for example, / and 6 At the same time, the value of the MDM signal at the outputs of the counter 17 in the moment is available. signal U, takes one of the possible values given in the table.

With the help of u, d, which is fed to the input of the parallel recording of the counter 17, the code present at the outputs of block 18 is recorded. The code at the outputs of block 18 specifying codes with | 11 6 has at 1000 and corresponds to the zero value of the MDM signal (table) . The value of the delta code and, is the control signal of the counter 17, i.e., with a single or zero value of the signal U, the counting direction of the block 17 will be respectively direct or reverse. At time 1, therefore, the contents of counter 17 (and it was equal to zero) with the arrival of the next clock pulse Ujo increases by one. Counter 17 works similarly at times, and C,. At time point C g, the signal U О changes the counting direction of block 17 by

five

eight

the opposite, due to which its content is reduced by one.

Thus, at the moment of time, the contents of the reversible counter 17 will be equal to the sum of (six) values of the one-bit code, in the interval C l and in this case

and-6) Z.U ,, M,

|

and corresponds to the difference in times of thinned samples

l a a

0 5 5

0

and, (g

 XK + I X K

 +5 - (+ 1) 4

approximate PCM signal. delta modulator of torus. The readout of the signal in the MDM format must be carried out by the presence of pulses at the output of the divider 19. The signal delay time in element 21 must be no less than the readout time of the MDM signal from the output of counter 17.

The formation of the MDM signal at odd (H is carried out in the same way as for even / m and is presented, for example, for (U 5 (Fig. 3) in the time interval about,

(U--

and, (g, b) jl and, b. -3,

which corresponds to the difference of PCM-bills, pro- duced by | i 5 times,

X ,, h X, - - +1 - (+ it) -3.

With an even conversion factor / U divider 19, the case is possible when and, О, and for odd | K - always and, 7 0. Therefore, when a two-pole analog signal UgjjCt) is applied to the input of the delta modulator, its fourth output 25 produces a signal in the MDM format with a switching quantization characteristic, which is even or odd (1 | corresponds to a quantizing characteristic with central suppression or central clipping of weak signals.

Block 18 task codes can serve as a register with a parallel output.

Claims (1)

Thus, when a two-pole analog input signal is applied, the delta modulator at the first output generates a signal in the format of linear delta modulation in the form of a one-bit binary code, at the second and third outputs - PCM-signals in the form of a direct code with a significant digit home, on the fourth outputs, a signal in the format of a multilevel delta modulation with a switchable quantizing characteristic as an additional code; on the fifth output, pulse signals that allow the reading of the MDM signal from the fourth output and the following frequencies th discretization modulation with multilevel delta. Invention Formula Delta-modulator for ATV. St. (f, characterized in that, in order to expand the field of application, by generating an output signal in a multilevel delta modulation format with a switchable quantizing characteristic, a second reversible counter, a divider with a programmable division factor, and a second and third delay elements are introduced into the delta modulator and the code setting unit, the outputs of which are connected to the installation inputs of the second reversible counter, the control input of which is connected to the output of the EXCLUSIVE OR element, the inputs of the divider with programmable the division factor and the second delay element are connected to the outputs O, respectively, of the clock pulse generator and the first delay element, the outputs of the second and third delay elements, respectively, are connected to the counting input and the input 5, the recording resolution of the second reversible counter, the outputs of which are the fourth outputs of the delta modulator, the output of the divider with programmable division factor is connected to the input of the third delay element and is the fifth output of the delta modulator. 0 / C Oinl Phie.g r g 2 j Г Г Г Г Г; # / U / (/ 7 / #