SU1506441A1 - Device for producing clock signals - Google Patents

Abstract

The invention relates to computing, in particular, to be used in data processing systems. A feature of the device is that it allows varying the duration of the cycle of generation of clock pulses. The aim of the invention is to expand the functionality by randomly varying the duration of the clock generation cycle. The goal is achieved by introducing the two AND elements, the OR element. 1 il.

Description

3150

In this case, the counting sequence from the outputs of the memory block 1 is fed to the address inputs of the memory block 3, forming the required sync signal sequence at the outputs 32-36 of the device. If a signal arrives at the stop A input A, the trigger 10 is set to 1, prohibiting the passage of signals from the outputs of the fixed memory unit 1 through the AND 5-9 elements of the first group, and the generation of clock pulses at the outputs 32-36 of the device stops. If a signal arrives at the start 11 of the device, the trigger 10 is reset to 0 and the generation of the cp pulses at the outputs 32-36 of the device continues from the place where the stop occurred.

If it is necessary to start the generation clock pulses from a certain place of the cycle, then the inputs to the inputs 27-31 of the device correspond, the code, in particular, it can be the code of the beginning of the cycle, and the synchronous input 23 of the recording device recording impulse will write this code In register 2. When a pulse is applied to the device start input 11, the trigger 10 is reset to O, which leads to a repeated use of a certain lecTa cycle.

Claims (1)

Invention Formula A DPP device for generating sync signals containing two blocks of a fixed memory, a register, the first and second groups of elements AND, a group of elements OR, a trigger, and the outputs of the first block of the permanent memory are connected respectively to the first inputs of the elements And the first group, the second "rye inputs of which are combined and section 1 the trigger output, the outputs of the elements AND of the first group are connected to the first inputs of the elements OR groups, the second inputs of which are connected respectively to the outputs of the elements AND of the second group, the first inputs of which are the device restart setpoint, the second inputs of the AND elements the second group is combined and connected to the direct output of the output, the reset input of O of which is the device start input, the trigger set input is the device stop input, the element outputs of the OR groups S are connected respectively to the information inputs of the register, the bit outputs of which are connected to the address inputs of the second block of permanent memory, the outputs of which are information outputs of the device, characterized in that with the purpose of expanding the functionality of the clock pulse generation cycle. , two elements OR are entered into it OR element, and the bit outputs of the register are connected respectively to the address inputs of the first memory block, inverse transducer The igger is connected to the first input of the first element AND, the second input of which is the synchronous input of the device, the direct output of the trigger is connected to the first input of the second element AND, the second input of which is the recording enable input of the device, the output of the first element AND is connected to the first input of the OR element, the second output of which is connected to the output of the second element I, the output of the IL element is connected to the input of the register recording. and Z1 2B GD 30 j / pz S iHt Lz ( l “/ F“ , Ig and Az