SU1487053A1 - Computer/subscriber interface - Google Patents

Description

The invention relates to computing and can be used to exchange information.

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between the computer and external devices. The aim of the invention is to increase the speed of the device. The device contains a generator of I pulses, the element NOT 2, the second element And 3, the element 4 delay, the first and third elements And 5.6, the second trigger 7, the driver 8 pulses, the fourth element And 9, the counter Yu, the element OR II, the decoder 12 , the first trigger 13, register 14, the first and second switches 15, 16. The invention provides for the exchange of information between the computer and the subscriber, I Il.

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The invention relates to computing and can be used for the exchange of information between computers and external devices.

The purpose of the invention is to increase the speed of the device.

The drawing shows the block diagram of the device.

The device contains a pulse generator 1, a HE element 2, a second IZ element, a delay element 4, the first and third elements AND 5 and 6, the second trigger 7, the pulse generator 8, the fourth element AND 9, the counter 10, the element OR 11, the decoder 12, first trigger 13, register 14, first, second switches 15 and 16, zero potential buses 17 and 18, single potential bus 19, input 20 for connecting a computer synchronization output, input 21 for connecting a computer reset output, input 22 for connecting an end of operation output subscriber ^ input 23 for connecting information output E VM, output 24 for connecting the subscriber's information input and output 25 for connecting the computer request input.

The device works as follows.

When the device is turned on, its input 21 receives a reset signal, which resets the counter. 10 and triggers 7 and 13 to zero state. Thus, at the output of the device, the request signal to the computer for information output (None. The device can operate in two modes: under the program control from the computer side — automatic, and under operator control — manual (step-by-step). These modes are set using the switch 16. When it closes on the device bus 18, the device is allowed to operate in a step-by-step mode, and when it closes on the bus 19, operation in the automatic mode is permitted.

Consider the operation of the device in automatic mode.

At the initial moment, when the switch 15 is turned on, the pulse generator 1 generates a pulse of a given length and polarity, which is fed to the input of the element NOT 2. The pulse duration is selected so that the trigger 13 has time to switch and all transients have ended. From the output of the element NOT 2, a pulse arrives at the first input of the element I 3, prohibiting its operation.

In addition, the pulse from the output of the generator 1 pulses is supplied to the first input element And 5 and to the synchronization input of the trigger 13 and sets it. As a result, the output of the trigger 13 is set to a signal that is fed to the synchronization input of the register 14, the second input of the element ‘.

And 6, the second input element And 5 and allows them to work. Thus, the pulse from the pulse generator 1 at the first input of the element I 5 passes the last one, and from its output it enters the synchronization input of the first trigger 7 and sets it. At the output of the trigger 7, a signal is generated which is fed to the input of the pulse shaper 8, which forms request signal in the computer at the output 25 of the device. The computer receives the request signal and responds with a byte of information at the device input 23 and a clock pulse at the device input 20. The information byte is written to register 14 and given to output 24 for transmission to the subscriber. The sync pulse arrives at the input of the AND 9 element and at the first input of the OR 11 element. From the output of the last one, the sync pulse arrives at the synchronization input of the trigger 7 and resets it. As a result, a request signal is removed at the output 25 of the device. From the output of the element And 9 sync pulse arrives at the second input of the element FROM. At the first input of the element I 3 there is a signal allowing the passage of the sync pulse. From the output of the last clock pulse is fed to the input element 4 delay. From the output of the latter, the clock pulse delayed by the subscriber’s time arrives at the first input of the third element AND 6. C. The output of the third element And 6 synchronizes the pulse at the second input of the first trigger 7 and cocks it. As a result, the driver of the 8 pulses generates a request signal in the computer. The cycle of information transfer is repeated.

Counter 10 is designed for counting ^- sync pulses. When the counter 10 overflows, a signal is generated at its output, which is fed to the second input of the element OR 11, and from its output to the zero input of the trigger 7 and resets the last one. As a result, the request signal is removed in the computer on

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outputting information on output 25. Overflow of counter 10 means that the subscriber’s memory is full and operator intervention is required. The request signal to the computer to output information on output 25 does not occur until counter 10 is reset by a general reset signal on input 21 of the device .

Signs of the end of operations from the subscriber arrive at the device input 22, which are decoded by the decoder 12. A signal appears at the output of the latter, which resets the trigger 13 if the signs of the end of the subscriber’s operations are fulfilled. These operations can be the lack of information at the device input, the end of the frame, the end of the tape, etc.

Consider the operation of the device in manual (step by step mode.

The principle of operation of the device in this mode is similar to that described, except that switching the switch 16 to the bus 18 blocks the passage of clock pulses from the device input 20 through the chain: element AND 9, element IZ, element 4 delays, element 6, and, accordingly, the installation trigger 7. Reset trigger 7 occurs, as in automatic mode, on its clock input through the element OR 11, the formation of a request signal in the computer to issue information occurs, as described, when switching switch 15 through the chain: generator 1 impulse owls ^ second AND gate 5, the first flip-flop 7 '

Claims (1)

Claim A device for interfacing a computer with a subscriber, comprising a pulse generator, a delay element, first, second. Triggers, a counter, a decoder, a register and a pulse shaper, the device input for connecting a computer synchronization output connected to the counter input of the counter register, the information input of which is connected to the input of the device for connecting the information output of the computer, the output of the register is connected to the output of the device for connecting the information input of the subscriber, exc Considering the fact that, in order to improve the speed of the device, the first to fourth elements AND, the OR element and the first, second switches are introduced into it, the fixed contact of the first and the first fixed contact of the second switch connected to the device zero potential bus, the moving contact of the first switch connected to the enable input of the pulse generator, the output of which is connected to the synchronization input of the first trigger, with the first input of the first element And through the element NOT with the first input of the second element And, the output of which through the delay element is connected to the first input of the third element And, the second inputs of the first, third elements, And soy. . dinene with the output of the first trigger, the input of the device for connecting the computer reset output is connected to the reset inputs of the first, second triggers and the counter, the outputs of the first, third elements And are connected respectively to the installation and information inputs of the second trigger, the output of which is through connecting the request for a computer input, the device input for connecting the synchronization output of a computer is connected to the first inputs of the fourth AND element and the OR element, the second input and output of which are connected: here, respectively, with the counter output and with the synchronization input of the second trigger, the second fixed contact of the second switch is connected to the unit potential bus, the movable contact of the second switch is connected to the second input of the fourth And element whose output is connected to the second input of the second element, And device for connecting the output end of the subscriber operation is connected to the input of the decoder, the output of which is connected to the information input of the First trigger.