SU1481756A1 - Digital accumulator with fractional variable capacity - Google Patents

Abstract

The invention relates to measuring and computing techniques and can be used to sum pulse sequences in digital frequency synthesizers with any discrete variation of the output synthesized frequency. The purpose of the invention is to increase speed and simplify the digital storage device. The digital storage device contains multiplexers 1 and 11, adders 2 and 12, registers 3-5, controlled frequency divider 13, code input 6, input 7 controls the integer value of the capacitance change, input 14 controls the fractional value of the capacitance, outputs 8 and 9, clock input 10, input 15 of the frequency division control. 1 il.

Description

The invention relates to the field of measuring and computing technology and can be used to sum pulse sequences in digital frequency synthesizers with any discrete change in the output synthesized frequency.

The purpose of the invention is to increase speed and simplify the digital storage device.

The drawing shows a functional diagram of a digital storage device with a fractional variable capacity.

The digital storage device contains a multiplexer 1, an adder 2, registers 3-5, an input 6 of a code (K), an input 7 for controlling the integral value of a change in the storage capacitor (M), an output 8 and 9, a clock input 10, a multiplexer 11, an adder 12, controlled frequency divider 13, fractional quantity change control input 14 (f}), frequency division gain control input 15.

The first information input of multiplexer 1 is input 6 of the code (K)

a digital accumulator whose outputs 8 and 9 are, respectively, the transfer output of the adder 2 and the output of the register 3, the clock input of which is connected to the clock input 10 of the digital accumulator (clock frequency / t). The second information input of multiplexer 1 is connected to the output of multiplexer 11, and the output of multiplexer 1 is connected to the input of register 4, the output of which is connected to the second input of adder 2, the first input and output of which are connected respectively to the output and input of register 3.

The input of register 5 is connected to the transfer output of adder 2 and the control input of register 4, the output of register 5 is connected to the control input of multiplexer 1 and the input of controlled frequency divider 13, the output of which is connected to the control input of multiplexer 11. The information inputs of multiplexer 11 are connected respectively to the first the input of the adder 12 and the output of the sum of the adder 12, the first input of which is connected to the control input 7 of the integer value of the capacitance change

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00

did eat

05

equal to the period of the output pulse overflow of the accumulator, and with the frequency determined by the division factor a, set programmatically to the input 15.

the storage device (M), and the second is connected to 2K-f-M-j-L and a new cycle begins at the input input 14 for controlling the fractional value of the storage capacity in which the capacity is changing the storage capacity (| 3). Clock is equal to r-m.

the inputs of registers 3-5 are combined and the sub-signal from the output of register 5 is supplied

checks to the clock input 10 of the accumulator - to the input of the controlled divider 13, which is (/ t). The drive operates as follows: it generates a pulse, in duration, by one. The adder 12 sums up the code M coming from the input 7, with the code p coming from the input 14, with the result that the sum code M + p is formed at the output of the adder 12. Thus, the first information channel is Thus only the M + P code is transmitted to the output of the multiplexing input of the multiplexer 11, only the code M arrives at the interim time, and the second time information, which is determined by the coefficient input code, Mf-p. If the signal is the division volume of the controlled divider 14, coming from the output of the controlled divider, i.e., once per cycle of frequency 13 at the control input of the multi- | 5 feeder. As a result, in (a-1) the cyclexer 11 is equal to zero, then on the second drive of the accumulator its capacity is equal to the information input of multiplexer 1, and in one cycle R-M-p. The M code will be received on average. While the transfer signal of adder 2 is zero, the output of multiplexer 1 will pass through the code K from the first information input of multi- plexer 1, this code is written to the register 4 in clock pulses, which at zero transfer from the adder 2 operates in the recording and storage mode. The storage capacitance value in a cycle is equal to

(K-M) (a-l) + (R-M-M R m p aJ

From this expression, it follows that the change of the code value p and the division ratio of the controlled divider 13 of the frequency information. The code K in the adder 2 is stored; you can get any discrete variable with the output code of the register 3, the code for changing the capacity of the storage device.

the sum is applied to the input of register 3 and the next clock pulse is written to register 3.

When in one of the operation cycles, the accumulator overflows, i.e. the sum value at the output of adder 2 reaches or exceeds the storage capacitance value, in adder 2 a residual L is formed, and at output 8 a transfer signal equal to logs This digital storage with a fractional variable capacity must meet the following conditions:

IP + TSZ T0;

tl + ti, o;

Tr, + tn “That;

TIS + TM. ,, - | -tsch 7vy,

where Tf5, TPVTpj is the delay in recording registers 3-5, respectively;

 , TP "- the delay time of the adder 2, adder-2 to the output of the transfer, respectively;

TMI, t „„ is the delay time of multiplexers I and 11.

Claims (1)

Claims of Invention Digital storage unit with a fractional rehearsal unit. This signal is fed to the control input of the type of register 4 operation 35 and puts it into the shift mode. In the next clock cycle, register 4 shifts the output information — the K code by one binary bit towards the higher bits, which is equivalent to the operation of multiplying the K code by two. Thus, the code corresponding to 2K will pass to the input of the adder 2 during this cycle of the accumulator operation. Same clock pulse to register 3 records the remainder of adder 2, in, "- a variable capacitance containing the first and second registers 5 - the transfer unit, on the output of the adder, the first and second multiplexer I will pass the code M with the second multiplexers, the first, second and third register the information input, the sum output and the controlled frequency divider, permator 2, the code of sum 2K is obtained. The signal information input of the first transfer mu num at output 8 becomes equalizer connected to the code input by a digital zero ; 0 zogo accumulator, the first and second output s is input to the control operatsiiustroystva views respectively connected to vyhoregistra 4 and transfers it to the transfer mode za- rows-first adder and the first storage .registra pisi and whose clock input is connected In the next cycle of operation of the accumulator with the clock input of the digital accumulator, in register 5 zero is written from the output and clock inputs of the second and third transfer adder 2, in register 4 - code 55 registers, the information input of the third re- M, in register 3 - code 2K + L, the output of the gist is connected to the transfer output of the first multiplexer I again receives the code K of the adder, and the output - with a clock input from the first information input, to the output controlled frequency divider and from the control of adder 2, a code is obtained by summing the input of the first multiplexer, equal to the period of the output pulse overflow of the accumulator, and with the frequency determined by the division factor a, set programmatically to the input 15. to the input of the controlled divider 13, which produces a pulse, by duration. Thus, the output of the multiplexer 11 passes the code M + P only at the time points determined by the division factor of the controlled divider 14, i.e. once for a cycle of work accumulated. As a result, in (a-1) accumulator operation cycles its capacity is equal, and in one cycle R-M-p. Medium to the input of the controlled divider 13, which produces a pulse, by duration. Thus, the output of the multiplexer 11 passes the code M + P only at the time points determined by the division factor of the controlled divider 14, i.e. once for a cycle of work accumulated. As a result, in (a-1) accumulator operation cycles its capacity is equal, and in one cycle R-M-p. Medium its value is the capacity of the accumulator for a cycles is (K-M) (a-l) + (R-M-M R m p aJ To ensure the operability of this digital storage device with a fractional variable capacity, the following conditions must be met: IP + TSZ T0; tl + ti, o; Tr, + tn “That; TIS + TM. ,, - | -tsch 7vy, where Tf5, TPVTpj is the delay in recording registers 3-5, respectively;  , TP "- the delay time of the adder 2, adder-2 to the output of the transfer, respectively; TMI, t „„ is the delay time of multiplexers I and 11. Invention Digital storage device with fractional capacity, containing the first and second adders, the first and second multi-pores, the first, second and third register output of which is connected to the information input of the second register, the output of which is connected to the first input of the first sum, math, second the input and output of which are connected respectively to the output and information input of the first register, the output of the controlled frequency divider is connected to the control input of the second multiplexer, the first information input of which is connected to p The first input of the second adder and with the control input is an integer value of the change in the capacity of the digital storage, while the second input of the second adder is connected to the control input the fractional value of the change in the digital storage capacity and the output to the second information input of the second multiplexer, and the information input of the controlled frequency divider is connected to the input of the control of the frequency division ratio of the digital storage, characterized in that, in order to increase the speed and simplify the device, the output the second multiplexer is connected to the second information input of the first multiplexer, and the transfer output of the first adder is connected to the control input of the type of operation of the second reg Stra.